Silicon Sacrificial Layer for Merged 3D NAND HAR Contacts
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Solution Overview
Problem
The increasing aspect ratio of contacts in three-dimensional (3D) NAND memory devices leads to higher fabrication costs due to the need for separate processing of different types of high aspect ratio contacts (HARCs), necessitating a sacrificial layer that is thermally stable and can be filled and removed effectively.
Innovation Solution
A method involving a deposition/etch/deposition process using a silicon-containing sacrificial layer, specifically amorphous silicon, to fill and cover top portions of contact holes, which is thermally stable during high temperature anneal and has etch selectivity from carbon-containing sacrificial layers, allowing for simultaneous fabrication of different types of HARCs and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If different types of high aspect ratio contacts are fabricated separately, then each contact type can be optimized individually, but fabrication cost significantly increases
Solution Approach 1:
The patent merges the fabrication of different types of high aspect ratio contacts (memory holes and contact holes) into a single simultaneous process. By forming both contact types in one fabrication step rather than separate steps, the patent reduces overall fabrication cost while maintaining the ability to optimize each contact type's dimensions and properties through the unified process parameters.
2Ease of manufacture
If a sacrificial layer is used to enable simultaneous fabrication of different HARCs, then fabrication cost decreases, but the sacrificial layer must be thermally stable at high temperature
Solution Approach 1:
The patent changes the material parameter of the sacrificial layer from conventional organic materials to silicon-containing material. This parameter change enables the sacrificial layer to withstand high temperatures during subsequent fabrication processes while remaining removable through selective etching, thus satisfying both the cost reduction goal and the thermal stability requirement.
3Ease of operation
If a carbon-containing sacrificial layer is used for memory holes, then it can be selectively removed, but it lacks thermal stability at high temperature anneal
Solution Approach 1:
The patent uses a composite material approach by combining silicon-containing sacrificial layer properties with the structural requirements of both memory holes and contact holes. The silicon-containing material provides both the thermal stability needed for high-temperature processing and the etch selectivity needed for subsequent removal, effectively replacing the carbon-containing sacrificial layer that lacked thermal stability.
4Ease of manufacture
If the critical dimension of contact holes is widened, then filling becomes easier, but the contact hole dimensions must be precisely controlled
Solution Approach 1:
The patent applies preliminary action by forming the silicon-containing sacrificial layer in advance within the contact holes before the final filling process. This preliminary sacrificial layer serves as a template that defines the contact hole dimensions and facilitates subsequent filling operations, while the dimensions are precisely controlled through the deposition process parameters of the sacrificial layer formation step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the cost-effective fabrication of various HARCs in 3D NAND memory devices by using a thermally stable silicon-containing sacrificial layer, reducing the complexity and expense associated with separate processing of each type of contact.
Implementation Method 1
simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process
Implementation Method 2
by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm
Implementation Method 3
can be thermally stable at high temperature
Implementation Method 4
performing a first removal process, the first removal process comprising selectively removing the carbon-containing sacrificial layers from the contact holes
Data Source
AI summary
A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.