Crystalline Silicon Liner Isolation for Dense Active Pattern Transistors
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Solution Overview
Problem
As semiconductor devices become highly integrated, there is a need to reduce the area of the upper surface of active patterns while maintaining their quality and ensuring sufficient space for forming transistors and contact plugs, with existing technologies facing challenges in achieving defect-free and efficient manufacturing processes.
Innovation Solution
A semiconductor device is manufactured with a silicon liner having a crystalline structure that covers the active pattern and substrate, an insulation layer formed on the liner, and an isolation pattern filling trenches adjacent to the active pattern, along with a transistor structure that includes a gate structure and impurity regions, allowing for the formation of contact plugs without reducing the active pattern's surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the area of the upper surface of active patterns is decreased to achieve high integration, then device integration density is improved, but the quality and defect-free status of active patterns deteriorates
Solution Approach 1:
A silicon liner layer is introduced as an intermediary between the active pattern and the gate insulation layer. This liner layer has a crystalline structure that improves the interface quality and reduces defects, allowing the active pattern area to be reduced for higher integration while maintaining or even improving the overall device reliability.
Solution Approach 2:
The crystalline structure of the silicon liner layer changes the physical and electrical parameters of the interface region. This structural transformation enables better charge carrier mobility and reduced interface states, compensating for the reduced active pattern area and maintaining device performance.
2Area of stationary object
If the area of the upper surface of active patterns is decreased, then space for transistors and contact plugs is optimized, but sufficient area for forming transistors and contact plugs is compromised
Solution Approach 1:
The solution extends the functional area into the vertical dimension by forming the gate structure and contact plugs at different heights and positions. The silicon liner layer provides a vertically extended interface that allows contact plugs to be formed through the liner to reach the active pattern, effectively utilizing three-dimensional space rather than being constrained to a two-dimensional planar area.
3Manufacturing precision
If a liner layer is formed to improve interface quality, then manufacturing complexity increases, but the process remains manageable
Solution Approach 1:
The silicon liner layer is formed by controlling deposition parameters and crystallization conditions to achieve the desired crystalline structure. By optimizing these parameters, the liner layer can be formed with consistent quality across different devices, improving interface characteristics while keeping the manufacturing process within acceptable complexity levels through parameter control rather than additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a semiconductor device with high performance and reduced surface roughness, enabling effective formation of transistors and contact plugs without surface area reduction, thus addressing the integration and defect challenges in existing technologies.
Implementation Method 1
A first silicon liner having a crystalline structure may be conformally formed on surfaces of the active pattern and the substrate
Implementation Method 2
A surface of the first silicon liner may be oxidized to form a second silicon liner
Data Source
AI summary
A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.