Silicon Liner Seed Layer for Low-Resistance Ru Interconnects
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Solution Overview
Problem
As semiconductor devices miniaturize, the wiring width in copper (Cu) interconnects becomes smaller than the mean free path of electrons, leading to increased resistance due to electron scattering, necessitating new materials and fabrication techniques for metal interconnects.
Innovation Solution
The method involves forming an amorphous silicon (a-Si) liner over a substrate with a dielectric and conductive layer, converting the a-Si liner into a silicon-containing layer with a metal, and depositing the metal over this layer using it as a seed layer, resulting in a RuSi layer that reduces electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If copper (Cu) wiring is used in miniaturized semiconductor devices, then the wiring width can be reduced to increase component density, but the electrical resistance increases due to electron scattering when wiring width becomes smaller than the mean free path of electrons
Solution Approach 1:
The patent changes the material parameters of the liner layer from conventional materials (titanium nitride, tantalum nitride) to silicon-based materials (amorphous silicon, polysilicon). This material parameter change enables the formation of low-resistance contact (below 0.1 ohm-mm²) in miniaturized wiring structures where the wiring width is smaller than the electron mean free path, thus resolving the contradiction between increased component density and increased electrical resistance
Solution Approach 2:
The patent creates a composite structure consisting of a silicon-based liner layer combined with metal interconnect materials. The silicon-based liner forms a low-resistance interface layer that, when combined with the metal wiring, creates a composite interconnect system with superior electrical conductivity compared to conventional liner materials, thereby maintaining low resistance even as wiring dimensions are reduced
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the electrical resistance of the Ru/liner stack by an order of magnitude compared to conventional liner materials, enhancing the conductivity and adhesion of ruthenium (Ru) metal in metal interconnects.
Implementation Method 1
a portion of the a-Si liner reacts with a portion of Ru to form RuSi at an initial stage of the vapor deposition process
Implementation Method 2
depositing the metal over the silicon-containing layer using the silicon-containing layer as a seed layer for the depositing
Data Source
AI summary
A method of processing a substrate includes forming an amorphous silicon (a-Si) layer over the substrate, where the substrate includes a dielectric layer and a conductive layer, and the a-Si liner covers a surface of the dielectric layer and a surface of the conductive layer. The method includes converting the a-Si liner into a silicon-containing layer including a metal; and depositing the metal over the silicon-containing layer using the silicon-containing layer as a seed layer for the depositing, where the metal deposited over the silicon-containing layer and the conductive layer are electrically connected.