Silicon-Based Mask With Dual Etching Rates

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Solution Overview

Problem

Existing silicon-based masks for high-resolution display products face challenges in achieving ultra-high resolution while maintaining low manufacturing costs and high efficiency, due to difficulties in etching uniformity and preventing over-etching.

Innovation Solution

A silicon-based mask comprising a first silicon wafer with a higher etching rate and a second silicon wafer with a lower etching rate, laminated one on another, where the second wafer acts as an automatic stop layer to prevent over-etching and improve manufacturing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a single silicon wafer is used for mask manufacturing, then the manufacturing process is simple, but etching uniformity is poor and over-etching cannot be prevented

Engineering Contradiction:
Improvemask manufacturing simplicityVSAvoidetching uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The mask is divided into two separate silicon wafers (first silicon wafer and second silicon wafer) with different etching rates. The first silicon wafer has a higher etching rate and forms the first via hole, while the second silicon wafer has a lower etching rate and forms the second via hole. This segmentation allows each wafer to be etched with appropriate control, preventing over-etching and improving etching uniformity while maintaining manufacturing simplicity.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If ultra-high resolution is achieved through high-resolution mask, then display quality improves, but manufacturing cost increases

Engineering Contradiction:
Improvemask resolutionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The invention changes the key parameter of etching rate by using two silicon wafers with different crystal orientations or doping concentrations. The first silicon wafer uses a higher etching rate parameter to efficiently form via holes, while the second silicon wafer uses a lower etching rate parameter to prevent over-etching. This parameter optimization enables ultra-high resolution mask manufacturing with controlled costs by reducing material waste and rework.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If etching rate is increased to improve manufacturing efficiency, then productivity improves, but over-etching occurs and precision deteriorates

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidetching control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The invention creates a dynamic etching process where the etching rate is adjusted in stages. The first silicon wafer is etched at a higher rate to quickly form via holes, improving productivity. Then the second silicon wafer is etched at a lower rate to precisely control the etching depth and prevent over-etching. This dynamic adjustment of etching rates across different stages maintains both high manufacturing efficiency and precise etching control.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed silicon-based mask enables high-efficiency and high-yield manufacturing of display panels with ultra-high resolution, while reducing production costs by utilizing monocrystalline silicon materials and optimizing etching processes.

Implementation Method 1

under a same etching condition, an etching rate of the second silicon wafer is smaller than an etching rate of the first silicon wafer

Methodology Applied
Scientific EffectEtching rate difference:

Data Source

PatentUS20250075304A1Silicon-based mask, manufacturing method, and display panel
Publication Date: 2025.03.06 BOE TECHNOLOGY GROUP CO LTD
  • US20250075304A1 patent drawing
  • US20250075304A1 patent drawing
  • US20250075304A1 patent drawing

AI summary

The present disclosure provides a silicon-based mask, a manufacturing method, and a display panel. The silicon-based mask includes a first silicon wafer and a second silicon wafer laminated one on another. The first silicon wafer includes a first via hole, the second silicon wafer includes a second via hole, an orthogonal projection of a wall of the first via hole onto the second silicon wafer surrounds the second via hole, and under a same etching condition, an etching rate of the second silicon wafer is smaller than an etching rate of the first silicon wafer.