Silicon Nanowire Memory Device Negative Differential Resistance
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Solution Overview
Problem
The challenge in developing semiconductor memory devices at nanometer scales is the fluctuation of tunneling barrier size, which affects current stability and makes it difficult to form devices smaller than the depletion layer width, particularly in SRAM memory cells using tunneling diodes, where achieving high density and stability is hindered by process fluctuations and impurity variations.
Innovation Solution
A semiconductor memory device is designed with silicon nanowires, featuring serially connected diodes exhibiting negative differential resistance and a select transistor, where the nanowires are 8 nm or less in thickness, leveraging phonon effects for stable operation and high memory capacity, and can be formed using SOI substrates with controlled thickness and doping for enhanced stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If tunneling diode devices are used to form high-density memory cells, then memory density is improved, but current stability deteriorates due to barrier size fluctuation
Solution Approach 1:
The patent changes the fundamental operating mechanism from tunneling diode-based current control to nanowire-based phonon scattering control. By using silicon nanowires with thickness of 10 nm or less, the device exploits phonon scattering effects that are intrinsic to the nanowire material and structure, making the current characteristics less sensitive to fabrication variations and impurity fluctuations.
2Quantity of substance
If device size is reduced to nanometer scale, then memory density is improved, but manufacturing precision deteriorates due to process fluctuations
Solution Approach 1:
The patent replaces the mechanical/tunneling-based diode structure with a nanowire structure that operates based on phonon scattering physics. This substitution enables the formation of reliable nano-meter order devices because the phonon scattering mechanism is inherently more robust to fabrication variations than tunneling barrier control, allowing consistent device performance even at 10 nm scale.
3Length of moving object
If tunneling barrier size is reduced, then device miniaturization is achieved, but current fluctuation increases
Solution Approach 1:
The patent fundamentally changes the physical mechanism from tunneling current (sensitive to barrier size) to phonon scattering current (intrinsic to nanowire material). By controlling nanowire thickness to 10 nm or less, the current characteristics are determined by phonon scattering processes that are less sensitive to dimensional variations, enabling stable operation at reduced device sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for stable operation and high memory capacity even at scaled-down sizes, reducing the impact of fabrication and impurity-related fluctuations, and enables the formation of nano-meter order devices with improved current-voltage characteristics.
Implementation Method 1
leveraging phonon effects for stable operation
Implementation Method 2
exhibiting negative differential resistances
Data Source
AI summary
According to an embodiment, a semiconductor memory device capable of stably operating even when an element is shrunk is provided. The semiconductor memory device of the embodiment includes: first and second diodes serially connected between power sources of two different potentials, formed by nanowires, and exhibiting negative differential resistances; and a select transistor connected between the first diode and the second diode. The nanowires are preferably silicon nanowires. The thickness of the silicon nanowires is preferably 8 nm or less.