Silicon Nanowire TFT Channel Layout for Higher Mobility Displays
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Solution Overview
Problem
Current thin film transistors used in display devices have poor characteristics, leading to suboptimal display quality in AMOLED and LCD devices.
Innovation Solution
A thin film transistor is designed with a grid-shaped active layer composed of silicon nanowires, a gate electrode extending in a perpendicular direction, and source and drain electrodes in contact with the nanowires, reducing interface traps and improving mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional thin film transistor structures are used, then manufacturing is simpler, but mobility characteristics and display quality deteriorate
Solution Approach 1:
The active layer is segmented into multiple independent silicon nanowires arranged in parallel, where each nanowire acts as an independent conduction channel. This segmentation increases the total active area and improves mobility characteristics while maintaining a manageable structural complexity through systematic arrangement
Solution Approach 2:
The invention transitions from a conventional planar active layer to a three-dimensional structure with silicon nanowires extending vertically from the substrate. This dimensional change increases the effective channel area without proportionally increasing the footprint, thereby improving mobility characteristics without excessive complexity increase
2Reliability
If the active layer is formed as a grid-shaped structure with silicon nanowires, then mobility characteristics improve, but manufacturing precision requirements increase
Solution Approach 1:
Protruding structures are formed in the dielectric layer before growing the silicon nanowires. These protruding structures serve as pre-positioned templates that guide the nanowire growth location and orientation, ensuring precise grid arrangement without requiring high-precision direct nanowire placement
Solution Approach 2:
The protruding structures in the dielectric layer act as intermediary elements between the substrate and the silicon nanowires. They provide a structured interface that facilitates controlled nanowire growth at specific locations and orientations, reducing the direct precision requirements for nanowire formation
3Productivity
If silicon nanowires are used in the active layer, then operating efficiency improves, but device complexity increases
Solution Approach 1:
The grid-shaped arrangement of silicon nanowires serves multiple functions simultaneously: it increases the active channel area for higher operating efficiency, maintains structural order through systematic patterning, and provides scalable geometry that can be adapted to different device sizes without fundamentally changing the structure
Solution Approach 2:
The invention optimizes parameters such as nanowire diameter, spacing, and density to achieve high operating efficiency. By carefully controlling these parameters within specific ranges, the device achieves improved performance without excessive complexity, as these are continuous parameters that can be tuned rather than discrete structural elements
Data Source
AI summary
A thin film transistor, a manufacturing method thereof, a display substrate, and a display device are provided. The thin film transistor includes: a substrate, an active layer, a gate, a source and a drain. The active layer is arranged on the substrate and formed as a grid, including silicon nanowires extending along a first direction, the active layer includes source and drain regions oppositely arranged along the first direction, and a channel region located therebetween. The gate is arranged on the substrate, and an orthographic projection of the gate onto the substrate overlaps with orthographic projections for silicon nanowires in the channel region onto the substrate. The source and drain are arranged on the substrate, the source contacts silicon nanowires in the source region, and the drain contacts silicon nanowires in the drain region.