Silicon Nitride Barrier Layer for 3D NAND Hydrogen Diffusion

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Solution Overview

Problem

In three-dimensionally arranged NAND flash memories, hydrogen diffusion from the layer stack into the interconnect layer during thermal steps negatively affects the electrical properties of transistors, leading to deterioration.

Innovation Solution

A silicon nitride layer is introduced between the interconnect layer and the layer stack, acting as a barrier to prevent hydrogen diffusion, and is formed using a low-pressure chemical vapor deposition method to ensure it does not contribute to hydrogen diffusion itself.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a layer stack is provided above an interconnect layer in a three-dimensionally arranged NAND flash memory, then the memory capacity and integration density are improved, but hydrogen diffusion from the layer stack into the interconnect layer during thermal steps causes deterioration of transistor electrical properties

Engineering Contradiction:
Improvememory capacity and integration densityVSAvoidelectrical properties of transistors
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A silicon nitride barrier layer is introduced between the layer stack and the interconnect layer to act as an intermediary that prevents hydrogen diffusion from the layer stack into the interconnect layer, thereby protecting the transistor electrical properties while maintaining the high-density three-dimensional structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The silicon nitride barrier layer creates an inert environment that blocks hydrogen atoms, preventing them from diffusing into the interconnect layer during thermal processing steps, thus maintaining the electrical integrity of transistors in high-capacity 3D NAND structures

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Reliability

If a barrier layer is introduced between the interconnect layer and the layer stack to prevent hydrogen diffusion, then the electrical properties of transistors are protected, but the device structure and manufacturing process become more complex

Engineering Contradiction:
Improveelectrical properties of transistorsVSAvoiddevice structure and manufacturing process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The barrier layer is formed by changing the deposition parameters (low-pressure chemical vapor deposition) to ensure the material properties prevent hydrogen diffusion while maintaining compatibility with existing manufacturing processes, thus protecting transistor electrical properties without significantly increasing device complexity

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively suppresses the deterioration of electrical properties in the interconnect layer by blocking hydrogen intrusion, maintaining the integrity of the transistors and improving the semiconductor device's performance.

Implementation Method 1

A silicon nitride layer is introduced between the interconnect layer and the layer stack, acting as a barrier to prevent hydrogen diffusion

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

formed using a low-pressure chemical vapor deposition method to ensure it does not contribute to hydrogen diffusion itself

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS11482489B2Semiconductor device and method of manufacturing the same
Publication Date: 2022.10.25 KIOXIA CORP
  • US11482489B2 patent drawing
  • US11482489B2 patent drawing
  • US11482489B2 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.