3D Memory Device Silicon Nitride Buffer Oxide Wafer Distortion
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Solution Overview
Problem
The increasing complexity and high aspect ratio in 3D memory devices lead to wafer bow or wafer distortion, posing a significant challenge in manufacturing high-integrity memory devices.
Innovation Solution
A memory device structure comprising a substrate, a stack layer with alternating dielectric and conductive layers, a channel structure with a charge storage structure, a silicon nitride layer surrounding the conductive layers, and a buffer oxide layer between the conductive and silicon nitride layers, where the silicon nitride layer improves the crystallization quality of the buffer oxide layer to lower the annealing temperature and prevent wafer distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the integrity of 3D memory devices is increased with complex film stack and high aspect ratio, then storage capacity and device performance are improved, but wafer bow or wafer distortion occurs
Solution Approach 1:
A buffer oxide layer is introduced as an intermediary layer between the silicon nitride layer and the conductive layers. This buffer layer acts as a mediator that prevents direct interaction between the silicon nitride layer and conductive layers, thereby preventing wafer bow and distortion while maintaining device integrity and performance
Solution Approach 2:
The patent employs a composite structure consisting of multiple materials including silicon nitride layer, buffer oxide layer, and conductive layers. This composite material approach allows optimization of each layer's properties to achieve both high device integrity and wafer flatness, resolving the contradiction between reliability and shape
2Shape
If the annealing temperature is reduced to prevent wafer distortion, then wafer flatness is improved, but the crystallization quality of the buffer oxide layer may deteriorate
Solution Approach 1:
The silicon nitride layer is formed as a preliminary layer before the buffer oxide layer. This preliminary action creates a suitable substrate that promotes proper crystallization of the buffer oxide layer even at lower annealing temperatures, thereby maintaining crystallization quality while enabling reduced annealing temperature for wafer flatness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively prevents wafer bow or wafer distortion by enhancing the crystallization quality of the buffer oxide layer, allowing for a lower annealing temperature and maintaining high integrity in memory devices.
Implementation Method 1
The silicon nitride layer is able to improve the crystallization quality of the buffer oxide layer to lower an annealing temperature of the post-deposition annealing (PDA) process
Implementation Method 2
lower an annealing temperature of the post-deposition annealing (PDA) process
Data Source
AI summary
Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.