Silicon Nitride Stopper for CMP Planarization
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Solution Overview
Problem
Conventional methods for manufacturing power semiconductor devices with RESURF structures face challenges in maintaining uniform thickness of insulating films and preventing substrate damage during the CMP planarization process, leading to variations in electrical characteristics and potential current leakage.
Innovation Solution
A method involving the formation of a silicon nitride film on a semiconductor substrate, followed by a ring-shaped trench creation, where a first silicon oxide film is applied to the trench inner surface, and a second silicon oxide film is planarized using the silicon nitride film as a stopper to prevent over-polishing and substrate damage, with a third silicon oxide film formed post-removal of the nitride film to fix interface charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP planarization is performed until substrate exposure to remove all insulating film, then uniform thickness is achieved, but substrate damage occurs leading to current leakage
Solution Approach 1:
A silicon nitride stopper film is formed on the substrate surface before depositing the insulating film. This preliminary action creates a physical barrier that prevents the CMP process from damaging the substrate while still allowing the insulating film to be planarized to a uniform thickness. The stopper film is removed after planarization, leaving the substrate intact.
Solution Approach 2:
The silicon nitride film acts as an intermediary layer between the CMP polishing surface and the substrate. It mediates the planarization process by providing a removable protective layer that enables uniform film thickness achievement without direct substrate contact during polishing, thus preventing substrate damage.
2Reliability
If CMP planarization is stopped before substrate exposure to preserve insulating film, then substrate damage is prevented, but thickness variation occurs causing color unevenness and etching controllability issues
Solution Approach 1:
The silicon nitride stopper film is deposited beforehand to create a uniform reference surface for CMP planarization. This preliminary structure allows the insulating film to be planarized uniformly without requiring the CMP to expose the substrate, thus maintaining both substrate integrity and film thickness uniformity.
Solution Approach 2:
The stopper film serves as an intermediary that enables the CMP process to achieve uniform planarization without removing all insulating film. It provides a consistent polishing target that ensures uniform thickness while preventing the substrate from being exposed and damaged.
3Reliability
If thick insulating film is formed on RESURF layer to maintain breakdown voltage, then electrical performance is improved, but level difference on substrate increases making subsequent processing difficult
Solution Approach 1:
Chemical mechanical polishing (CMP) is used to replace traditional mechanical planarization methods. CMP provides superior planarity control and can uniformly remove material across the entire substrate surface, including the thick insulating film on the RESURF layer, without causing the level differences that plague mechanical methods.
Solution Approach 2:
The silicon nitride stopper film is formed before depositing the thick insulating film. This preliminary structure enables the subsequent CMP process to planarize the thick film uniformly while preventing substrate damage, thus maintaining both the required film thickness for breakdown voltage and the substrate planarity for subsequent processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent film thickness, prevents substrate damage, and improves controllability and electrical characteristics by fixing interface charges, thereby enhancing the manufacturing process and device performance.
Implementation Method 1
planarizing the second silicon oxide film by using the silicon nitride film as a stopper
Implementation Method 2
forming a first silicon oxide film on an inner surface of the trench
Implementation Method 3
forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench
Implementation Method 4
removing the silicon nitride film, and then forming a third silicon oxide film in a region in which the silicon nitride film is removed
Data Source
AI summary
A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.