Carbon-Doped Silicon Oxide Liner for Fin Oxidation Resistance
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Solution Overview
Problem
The challenge in the formation of FinFETs is to achieve high oxidation resistance for semiconductor strips during the formation of Shallow Trench Isolation (STI) regions, as existing methods fail to adequately protect these strips from oxidation, which can affect the performance and reliability of integrated circuits.
Innovation Solution
The formation of SiOCN films followed by anneal processes to convert them into silicon oxide layers, which provide excellent oxidation resistance and protect the semiconductor strips from oxidation, using Atomic Layer Deposition (ALD) cycles and subsequent annealing steps to create a dense silicon oxide layer with controlled carbon and nitrogen content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional STI formation methods are used, then the process is simple and fast, but the semiconductor strips are not adequately protected from oxidation
Solution Approach 1:
An isolation liner layer is formed on the semiconductor strip surfaces before the STI region formation process begins. This preliminary protective layer prevents oxidation of the semiconductor strips during subsequent processing steps, addressing the oxidation resistance problem while maintaining a relatively straightforward process sequence.
Solution Approach 2:
The isolation liner acts as an intermediary protective layer between the semiconductor strips and the oxidizing environment during STI formation. This intermediate layer provides the necessary oxidation protection without requiring fundamental changes to the STI process itself.
2Ease of manufacture
If no isolation liner is used, then the process is simpler, but the semiconductor strips oxidize during STI formation
Solution Approach 1:
The isolation liner is applied in advance to counteract the harmful oxidizing effects that would otherwise occur during STI formation. This preliminary protective measure prevents oxidation damage before it can affect the semiconductor strips, while adding only one additional process step.
3Reliability
If the isolation liner is made thicker, then oxidation protection is improved, but the STI region formation becomes more complex
Solution Approach 1:
The isolation liner is applied selectively only to the semiconductor strip surfaces where oxidation protection is needed, rather than uniformly throughout the entire structure. This localized approach provides effective protection while minimizing interference with the STI region formation precision and avoiding unnecessary material accumulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The resulting silicon oxide layers effectively prevent oxidation of semiconductor strips, enhancing the reliability and performance of FinFETs by maintaining the integrity of the semiconductor materials and ensuring proper device operation.
Implementation Method 1
The formation of SiOCN films followed by anneal processes to convert them into silicon oxide layers
Implementation Method 2
convert them into silicon oxide layers, which provide excellent oxidation resistance and protect the semiconductor strips from oxidation
Implementation Method 3
using Atomic Layer Deposition (ALD) cycles and subsequent annealing steps to create a dense silicon oxide layer
Data Source
AI summary
An integrated circuit structure includes a bulk semiconductor region, a first semiconductor strip over and connected to the bulk semiconductor region, and a dielectric layer including silicon oxide therein. Carbon atoms are doped in the silicon oxide. The dielectric layer includes a horizontal portion over and contacting a top surface of the bulk semiconductor region, and a vertical portion connected to an end of the horizontal portion. The vertical portion contacts a sidewall of a lower portion of the first semiconductor strip. A top portion of the first semiconductor strip protrudes higher than a top surface of the vertical portion to form a semiconductor fin. The horizontal portion and the vertical portion have a same thickness. A gate stack extends on a sidewall and a top surface of the semiconductor fin.