Silicon Oxide Interface Layer for Dielectric Stack Adhesion
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Solution Overview
Problem
Dielectric delamination occurs at the silicon carbide etch stop interface to the ultra low k (ULK) dielectric layer in copper interconnect structures, leading to electrical shorting due to copper migration, and existing solutions like creating an interface layer during ULK deposition or helium plasma treatment are difficult to control and ineffective.
Innovation Solution
Forming a thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric layer in semiconductor devices to improve adhesion, which can be achieved by depositing the silicon oxide layer in a first processing chamber and the ultra low-k dielectric layer in a second chamber, using processes like CVD, LPCVD, or PECVD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interface layer is created during ULK deposition to improve adhesion, then adhesion between etch stop layer and ULK dielectric is improved, but plasma instability occurs resulting in higher defectivity and manufacturability issues
Solution Approach 1:
The patent applies preliminary action by forming the silicon oxide interface layer during the etch stop deposition process rather than during ULK deposition. This shifts the timing of interface layer creation to an earlier stage, allowing the ULK deposition to proceed without plasma instability while still achieving improved adhesion through the pre-formed silicon oxide layer.
Solution Approach 2:
The patent uses an intermediary approach by introducing a silicon oxide layer as a mediating interface between the etch stop layer and ULK dielectric. This intermediary layer is formed during etch stop deposition and serves as a stable bonding interface that improves adhesion without causing plasma instability during ULK deposition.
2Reliability
If Helium plasma treatment is used to improve adhesion, then some adhesion improvement is achieved, but the technique is not effective and dependent on silicon carbide properties/composition
Solution Approach 1:
The patent applies parameter changes by transitioning from Helium plasma treatment to forming a silicon oxide interface layer during etch stop deposition. This changes the fundamental mechanism from plasma treatment to in-situ oxide formation, which is less dependent on silicon carbide composition and provides more consistent adhesion improvement across different material variations.
Solution Approach 2:
The silicon oxide layer serves as a universal intermediary that bridges the etch stop layer and ULK dielectric regardless of the specific silicon carbide composition. This intermediary approach provides consistent adhesion improvement across different silicon carbide properties, unlike Helium plasma treatment which is highly dependent on material composition.
3Device complexity
If no interface layer is used, then the dielectric stack structure is simpler, but dielectric delamination occurs at the silicon carbide etch stop interface leading to electrical shorting
Solution Approach 1:
The patent applies preliminary action by forming the silicon oxide interface layer during the etch stop deposition process itself, rather than adding a separate layer during ULK deposition. This integrates the interface layer formation into an existing process step, minimizing additional complexity while preventing delamination and electrical shorting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances adhesion between the etch stop layer and the ultra low-k dielectric layer, reducing defectivity and manufacturability issues, and results in a small reduction in capacitance due to a lower dielectric constant, while stabilizing plasma reactions.
Implementation Method 1
forming a thin silicon oxide layer over the etch stop layer in a first processing chamber
Implementation Method 2
using processes like CVD, LPCVD, or PECVD
Implementation Method 3
stabilizing plasma reactions
Data Source
AI summary
In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.