Heterogeneous Silicon and Oxide Semiconductor Integration on Sapphire
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Solution Overview
Problem
Conventional semiconductor devices with power devices and control circuits packaged in a single chip face challenges in reducing size due to high surface area occupation by power devices, making cost reduction and size minimization difficult, especially when using silicon-based materials, and the integration of wide band gap materials like SiC and GaN as discrete devices complicates manufacturing and increases component count.
Innovation Solution
A semiconductor device and manufacturing method that integrates a silicon layer and an oxide semiconductor layer on a sapphire substrate, allowing for the formation of both silicon and oxide semiconductor devices on a single chip, with the oxide semiconductor layer being formed adjacent to the silicon layer, enabling a power device and control circuit to be integrated on a single chip, reducing chip size and surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power devices are configured using silicon-based materials in a single chip, then the chip can be manufactured with conventional processes, but the surface area occupied by power devices becomes excessively large (60-90% of chip area)
Solution Approach 1:
The patent changes the material parameter from silicon to wide band gap materials (SiC, GaN) for power devices, which fundamentally alters the electrical properties and allows for much smaller device footprints while maintaining or improving performance. This material parameter change enables the resolution of the contradiction between ease of manufacture and chip area reduction.
Solution Approach 2:
The patent employs a layered structure with silicon layer for control circuits and wide band gap material layer for power devices, stacking different material systems vertically. This dimensional approach allows integration of heterogeneous materials and circuits without requiring large planar area, thus reducing chip surface area while maintaining manufacturability through standardized layering processes.
2Area of stationary object
If wide band gap materials (SiC, GaN) are used for power devices to reduce ON-resistance and chip size, then device performance improves and chip size reduces, but the devices become discrete components requiring separate packaging
Solution Approach 1:
The patent merges previously separate discrete components (power devices made from wide band gap materials and control circuits made from silicon) into a single integrated chip structure. By stacking the wide band gap material layer directly on the silicon substrate and forming both power devices and control circuits on the same chip, the patent combines multiple functions into one device, reducing packaging complexity while maintaining the area benefits of wide band gap materials.
Solution Approach 2:
The patent uses a composite structure combining silicon substrate with wide band gap material layers (SiC or GaN). This composite material approach allows the chip to leverage the low ON-resistance and high breakdown voltage of wide band gap materials while maintaining compatibility with conventional silicon-based control circuit fabrication, thereby reducing manufacturing complexity compared to entirely new material systems.
3Reliability
If power devices and control circuits are packaged separately as discrete devices, then each device can be optimized independently, but the number of component points increases and manufacturing management becomes complicated
Solution Approach 1:
The patent merges power devices and control circuits into a single integrated chip, eliminating the need for separate packaging and interconnections. This integration reduces the number of component points and simplifies manufacturing management while maintaining the ability to optimize each device type through dedicated material layers and process steps.
Solution Approach 2:
The patent segments the chip into distinct functional regions: a first region with silicon-based control circuits and a second region with wide band gap material power devices. This spatial segmentation allows independent optimization of each device type through material-specific process steps while maintaining integration on a single chip, thereby reducing component management complexity.
Data Source
AI summary
A semiconductor device having reduced size, and a manufacturing method of the semiconductor device, where the semiconductor device has a silicon layer provided in a first region on a sapphire substrate, and a silicon device formed on the silicon layer. An oxide semiconductor layer is provided in a second region on the sapphire substrate, and an oxide semiconductor device is formed in the oxide semiconductor layer. The silicon device is connected to the oxide semiconductor device by plural wiring lines formed in a wiring line layer.