Silicon Oxide Spacer Structure for Planarization-Free Resistive Memory

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Solution Overview

Problem

Resistive memory cells in nanometer dimensions face challenges in integration into back-end structures due to variations in topography and the need for planarization processes, which affect device yield and processing costs.

Innovation Solution

Incorporation of silicon oxide plates as insulating structures between bottom conductive structures and an underlying etch-stop dielectric layer, with controlled thickness reduction to enhance uniformity and eliminate planarization, facilitating integration and scaling of resistive memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If resistive memory cells are integrated into back-end structures, then device functionality is achieved, but topography variations and planarization requirements increase device complexity and processing costs

Engineering Contradiction:

Improvedevice yieldVSAvoidplanarization process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A planarization layer is formed over the resistive memory cells before subsequent processing steps. This preliminary planarization action creates a flat surface that eliminates topography variations, allowing standard back-end processing to proceed without additional planarization steps and improving device yield

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The planarization layer acts as an intermediary between the non-planar resistive memory cells and the subsequent back-end processing steps. This intermediate layer absorbs topography variations and provides a uniform surface for metal deposition and patterning, reducing device complexity

Inventive Principle:

Principle #24Intermediary (Mediator)

2Area of moving object

If resistive memory cells are scaled to nanometer dimensions, then device density is improved, but integration difficulty and processing costs increase

Engineering Contradiction:

Improvememory cell areaVSAvoidintegration ease

Core Design Contradiction:

Area of moving objectVSEase of manufacture

Solution Approach 1:

The resistive memory cell structure is segmented into distinct functional layers including bottom electrode, memory material, top electrode, and planarization layer. This segmentation allows each layer to be optimized independently for nanometer scaling while maintaining ease of manufacture through standardized deposition and patterning processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory material layer undergoes parameter changes through controlled oxidation or reduction processes that create conductive filaments. By controlling the oxidation state and stoichiometry of the memory material, the device achieves nanometer-scale functionality with improved integration ease

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12588429B2Resistive memory device including a silicon oxide base spacer and methods for forming the same

Publication Date: 2026.03.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.