Carbon-Doped Silicon Oxide STI Liner for Fin Oxidation Resistance
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Solution Overview
Problem
The formation of Shallow Trench Isolation (STI) regions in Fin Field-Effect Transistors (FinFETs) faces challenges in achieving adequate oxidation resistance, which can lead to the oxidation of semiconductor strips, compromising the integrity and performance of the transistors.
Innovation Solution
The formation of SiOCN films followed by anneal processes to convert them into silicon oxide layers, providing excellent oxidation resistance and protecting the semiconductor strips from oxidation, is implemented. This involves Atomic Layer Deposition (ALD) cycles using Hexachlorodisilane (HCD) and triethylamine, followed by oxygen pulsing and annealing to form a dense silicon oxide layer with controlled carbon and nitrogen content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional oxide formation methods are used in STI region formation, then the process is simple and fast, but the oxidation resistance is inadequate leading to semiconductor strip oxidation
Solution Approach 1:
An isolation liner is formed prior to filling the STI region with oxide material. This preliminary liner layer is deposited on the trench walls before the main oxide fill, creating a protective barrier that prevents oxidation of the semiconductor strips during subsequent processing steps.
Solution Approach 2:
The STI structure employs a composite construction with an isolation liner layer and an oxide region layer. The isolation liner serves as a protective interface between the oxide material and the semiconductor strip, combining the benefits of both materials for optimal oxidation resistance.
2Ease of manufacture
If the STI region is formed without an isolation liner, then the process is simpler, but the semiconductor strips are vulnerable to oxidation compromising transistor integrity
Solution Approach 1:
The isolation liner is deposited as a preliminary protective layer on the trench walls before the oxide fill is introduced. This advance preparation creates a protective barrier that prevents direct contact between the oxide material and semiconductor strip, eliminating oxidation damage risk.
Solution Approach 2:
The isolation liner acts as an intermediary layer between the oxide region and the semiconductor strip. This intermediate layer prevents direct interaction that would cause oxidation, serving as a protective mediator while allowing the STI structure to function as intended.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The resulting silicon oxide layers demonstrate enhanced oxidation resistance, preventing undesired oxidation of semiconductor strips and ensuring the reliability and performance of FinFETs, even at smaller dimensions.
Implementation Method 1
Atomic Layer Deposition (ALD) cycles using Hexachlorodisilane (HCD) and triethylamine
Implementation Method 2
followed by oxygen pulsing and annealing to form a dense silicon oxide layer
Implementation Method 3
demonstrate enhanced oxidation resistance, preventing undesired oxidation of semiconductor strips
Data Source
AI summary
An integrated circuit structure includes a bulk semiconductor region, a first semiconductor strip over and connected to the bulk semiconductor region, and a dielectric layer including silicon oxide therein. Carbon atoms are doped in the silicon oxide. The dielectric layer includes a horizontal portion over and contacting a top surface of the bulk semiconductor region, and a vertical portion connected to an end of the horizontal portion. The vertical portion contacts a sidewall of a lower portion of the first semiconductor strip. A top portion of the first semiconductor strip protrudes higher than a top surface of the vertical portion to form a semiconductor fin. The horizontal portion and the vertical portion have a same thickness. A gate stack extends on a sidewall and a top surface of the semiconductor fin.