Display Pixel Circuit Using Silicon and Oxide TFTs for Low Power

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Solution Overview

Problem

Current display devices face challenges in achieving high integration and low power consumption while accurately controlling light emission and luminescence levels, primarily due to limitations in the design and materials used in thin-film transistors (TFTs).

Innovation Solution

The implementation of a display device structure that incorporates both silicon semiconductor and oxide semiconductor TFTs, along with a specific arrangement of power supply voltage lines, data lines, and capacitors, enhances integration and reduces power consumption by optimizing the electrical connections and layer configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of TFTs electrically connected to one display element is increased to accurately control light emission and luminescence level, then the control precision is improved, but the device complexity increases

Engineering Contradiction:
Improvecontrol precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The pixel circuit is divided into multiple TFTs (first TFT, second TFT, third TFT, fourth TFT) with specialized functions. Each TFT is responsible for specific control tasks (switching, driving, compensation), enabling precise control of light emission and luminescence level while maintaining manageable circuit complexity through functional segmentation.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If more TFTs are integrated into the display device to improve control accuracy, then the control precision is improved, but the power consumption increases

Engineering Contradiction:
Improvecontrol precisionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

Different TFTs use different semiconductor materials optimized for their specific functions: silicon semiconductor for switching TFTs requiring fast response, and oxide semiconductor for driving TFTs requiring low leakage current. This local optimization enables precise control while minimizing overall power consumption by matching material properties to functional requirements.

Inventive Principle:
Principle #3Local quality

3Device complexity

If silicon semiconductor TFTs are used to achieve high integration, then the device complexity is reduced, but the power consumption increases

Engineering Contradiction:
Improveintegration degreeVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The display device employs a composite semiconductor structure combining silicon semiconductor and oxide semiconductor in different TFTs. Silicon semiconductor provides high integration capability and fast switching, while oxide semiconductor provides low leakage current and low power consumption. This composite approach resolves the contradiction between integration degree and power consumption by leveraging the complementary strengths of different semiconductor materials.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS11910675B2Display device
Publication Date: 2024.02.20 SAMSUNG DISPLAY CO LTD
  • US11910675B2 patent drawing
  • US11910675B2 patent drawing
  • US11910675B2 patent drawing

AI summary

A display device includes a first thin-film transistor (TFT) including a first semiconductor layer including silicon semiconductor and a first gate electrode insulated from the first semiconductor layer, a first interlayer insulating layer covering the first gate electrode, a second TFT arranged on the first interlayer insulating layer and including a second semiconductor layer including oxide semiconductor and a second gate electrode insulated from the second semiconductor layer, a second interlayer insulating layer covering the second gate electrode, a first power supply voltage line arranged on the second interlayer insulating layer, a first planarization layer covering the first power supply voltage line, and a data line arranged on the first planarization layer and at least partially overlapping the first power supply voltage line.