Silicon Oxynitride Stress Layer for Thin Semiconductor Warpage
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Solution Overview
Problem
As semiconductor devices become thinner, warpage defects significantly impact their reliability, and existing methods are inadequate in effectively controlling and suppressing warpage.
Innovation Solution
A semiconductor device structure incorporating a crystalline silicon layer, an amorphous silicon layer, and a dielectric layer with compressive stress, formed through plasma treatment, to relieve stress and prevent warpage, where the dielectric layer is made of silicon oxynitride and strategically positioned to offset thermal expansion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of the semiconductor device is decreased to achieve light, thin, and miniaturized packages, then the device size is reduced, but warpage defects increase and reliability deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the stress state of the dielectric layer from tensile to compressive, and by controlling the thickness ratio between the amorphous silicon layer and crystalline silicon layer. These parameter changes enable the thin semiconductor device to maintain structural stability and reduce warpage, thereby improving reliability while keeping the device thin.
Solution Approach 2:
The patent uses composite materials by combining crystalline silicon and amorphous silicon in a layered structure. The amorphous silicon layer with compressive stress compensates for the tensile stress in the crystalline silicon layer, creating a balanced stress distribution that prevents warpage in thin devices.
2Ease of manufacture
If a dielectric layer with tensile stress is used in conventional structures, then manufacturing is simplified, but warpage occurs due to thermal expansion differences
Solution Approach 1:
The patent applies preliminary anti-action by introducing a compressive stress layer (amorphous silicon layer) before the device operates. This compressive stress pre-compensates for the tensile stress that would otherwise cause warpage during thermal cycling, thereby preventing shape instability while maintaining manufacturing feasibility.
Solution Approach 2:
The patent changes the stress parameter of the dielectric layer from tensile to compressive, and optimizes the thickness parameters of the amorphous silicon layer. This parameter optimization enables the dielectric layer to counteract thermal expansion stress, preventing warpage while maintaining ease of manufacture through standard plasma deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively reduces warpage defects and enhances the reliability of semiconductor devices by generating compressive stress that counters thermal expansion-related stress, thereby improving the overall performance and stability of the devices.
Implementation Method 1
a dielectric layer extending along a surface of the amorphous silicon layer, including silicon oxynitride, and having compressive stress
Implementation Method 2
offset thermal expansion differences
Implementation Method 3
formed through plasma treatment, to relieve stress and prevent warpage
Data Source
AI summary
The present disclosure relates to semiconductor devices and semiconductor packages. One example semiconductor device includes a crystalline silicon layer, an amorphous silicon layer on the crystalline silicon layer and extending along a first surface of the crystalline silicon layer, and a dielectric layer on the amorphous silicon layer and extending along a surface of the amorphous silicon layer. The dielectric layer includes silicon oxynitride and has compressive stress.