Silicon Passivation Layers on Germanium and III-V Devices
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Solution Overview
Problem
Current methods for forming gate dielectric interfacial layers on Ge or III-V semiconductor devices face challenges due to chemical and thermal instabilities of AsOx and GeO2, leading to low electron mobility in n-MOSFETs due to high trap density and electron scattering.
Innovation Solution
A method involving atomic layer deposition of a silicon passivation layer on a germanium or III-V semiconductor surface, followed by a high-k dielectric layer, is used to reduce trap density, with the silicon layer deposited at a temperature below 400°C to prevent interdiffusion, and the substrate kept under vacuum to avoid exposure to air.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AsOx or GeO2 interfacial layers are used with deposited high-k dielectric materials, then the interface can be formed on Ge or III-V semiconductor surfaces, but chemical and thermal instabilities occur leading to high trap density and low electron mobility
Solution Approach 1:
A silicon interfacial layer is introduced as an intermediary between the Ge or III-V semiconductor surface and the high-k dielectric material. This silicon layer acts as a stable buffer that prevents direct interaction between the unstable AsOx/GeO2 layers and the high-k dielectric, eliminating chemical and thermal instabilities while maintaining good interface quality and high electron mobility.
Solution Approach 2:
The gate stack employs a composite structure combining silicon interfacial layer with high-k dielectric materials. This composite approach leverages the stability and compatibility of silicon with both Ge/III-V surfaces and high-k dielectrics, creating a multi-layer system that achieves both interface stability and high electron mobility performance.
2Manufacturing precision
If silicon layer is deposited at high temperature to ensure complete coverage, then deposition quality improves, but interdiffusion of silicon with germanium or III-V surface occurs degrading the interface
Solution Approach 1:
The deposition temperature parameter is optimized to a specific range that enables complete silicon layer coverage of the semiconductor surface while remaining below the threshold temperature that would cause interdiffusion. This parameter optimization ensures both complete coverage and interface compositional stability without requiring extreme temperatures.
3Ease of operation
If the substrate is exposed to air during processing, then handling is simplified, but oxidation of the silicon interfacial layer occurs increasing trap density
Solution Approach 1:
The processing is conducted in an inert atmosphere or vacuum environment that prevents oxidation of the silicon interfacial layer. This controlled atmosphere eliminates exposure to oxygen and moisture during critical processing steps, preventing oxide formation and associated trap density increases while maintaining ease of operation through standardized inert processing procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high electron mobility in germanium and III-V n-MOSFETs by reducing trap density near the conduction band and maintaining the beneficial properties of the silicon interfacial layer.
Implementation Method 1
a silicon layer is deposited on a substrate having a germanium or III-V semiconductor surface via an atomic layer deposition process
Implementation Method 2
the silicon layer is deposited at a temperature to avoid interdiffusion of silicon with the germanium or III-V semiconductor surface
Implementation Method 3
the substrate surface is cleaned by atomic hydrogen cleaning prior to depositing the silicon layer
Data Source
AI summary
Described are apparatus and methods for forming silicon interfacial layers on germanium or III-V materials. Such silicon layers may be deposited by atomic layer deposition at specific temperatures to avoid interdiffusion of silicon and the germanium or III-V material.