Silicon-Containing Patterning Stack for Tight CD Uniformity
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Solution Overview
Problem
As semiconductor fabrication processes require smaller process windows, the decreasing pitch between elements and shrinking feature dimensions pose challenges in achieving high-quality pattern density and critical dimension uniformity using traditional optical masks and photolithography equipment.
Innovation Solution
The method involves a multi-layer patterning stack comprising a carbon-containing layer, a silicon-containing layer, and a photosensitive layer, which are deposited and patterned using advanced lithography techniques such as EUV lithography. This approach improves patterning metrics like line width roughness (LWR) and local critical dimension uniformity (LCDU) by utilizing materials with high density, hardness, and etch selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional optical masks and photolithography equipment are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to inability to achieve desired pitch and critical dimension uniformity
Solution Approach 1:
The patent divides the patterning process into multiple sequential steps including mandrel formation, spacer deposition, and iterative patterning cycles. Each step creates a portion of the final pattern, allowing complex high-precision patterns to be built from simpler intermediate structures that are within the capabilities of existing lithography equipment.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structures by forming spacers on the sidewalls of mandrels. This vertical dimension enables pitch multiplication and achieves critical dimensions smaller than the lithography resolution limit through self-aligned processes.
2Productivity
If pitch between elements is decreased to increase functional density, then productivity is improved, but manufacturing precision deteriorates due to difficulty in achieving desired spacing
Solution Approach 1:
The spacer formation process is self-aligned, where the spacer width is determined by the deposition thickness rather than lithographic patterning. This self-defined dimensioning automatically ensures uniform pitch spacing without requiring precise alignment, enabling high functional density with controlled spacing.
Solution Approach 2:
The patent controls pitch by adjusting deposition parameters such as spacer material thickness and composition rather than relying on lithographic resolution. By changing the deposition thickness parameter, the pitch between elements is precisely controlled independent of optical limitations.
3Area of moving object
If feature dimensions are shrunk to increase integration, then area is reduced, but manufacturing precision deteriorates due to challenges in maintaining pattern quality at smaller scales
Solution Approach 1:
The patent performs preliminary planarization and surface preparation steps before depositing spacer materials. This preliminary action ensures uniform deposition thickness across the substrate, which directly determines spacer width and thus final feature dimensions. The preliminary preparation maintains pattern quality even as feature sizes shrink.
Solution Approach 2:
The patent uses composite spacer structures with different materials having complementary properties. For example, a first spacer material provides structural support while a second material provides etch selectivity or adhesion properties. This composite approach maintains pattern integrity and quality at reduced feature dimensions by optimizing each material's contribution to overall performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described method enhances pattern quality by reducing line edge roughness and improving local critical dimension uniformity, allowing for more precise and dense feature formation in semiconductor devices, thereby addressing the challenges of smaller process windows and shrinking dimensions.
Implementation Method 1
a silicon-containing layer is formed over the organic bottom layer using a deposition process providing precursors delivered toward a surface of the organic bottom layer and chemically modifying the precursors to obtain the silicon-containing layer on the surface
Implementation Method 2
A portion of the resist layer is exposed to a radiation to provide a patterned resist layer
Implementation Method 3
A portion of the silicon-containing layer uncovered by the patterned resist layer is etched to form a patterned silicon-containing layer
Data Source
AI summary
In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.