Silicon Phosphide Source/Drain Doping for Low-Leakage FinFETs
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, challenges arise in reducing leakage and drain-induced barrier loading (DIBL) while maintaining high dopant concentrations in source/drain regions, which affects device performance and integration density.
Innovation Solution
The use of a single material doped with low-diffusivity dopants, such as phosphorus, arsenic, and carbon, for source/drain regions in FinFETs, which reduces leakage and DIBL without requiring an additional source/drain layer, allowing for increased volume and improved DC gain and oscillator speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high dopant concentrations are used in source/drain regions to improve device performance, then conductivity is improved, but leakage and drain-induced barrier loading (DIBL) increase
Solution Approach 1:
The patent applies local quality by using different dopant types in different regions: phosphorus (high diffusivity) is used in the bulk source/drain regions to achieve high conductivity, while carbon (low diffusivity) is specifically introduced at the interface regions adjacent to the channel to suppress leakage and DIBL. This spatial differentiation of dopant properties resolves the contradiction between achieving high conductivity and minimizing harmful leakage effects.
Solution Approach 2:
The patent employs composite doping strategy by combining multiple dopants (phosphorus and carbon) with different diffusivity characteristics in the same source/drain region. This composite approach allows the region to simultaneously exhibit high conductivity (from phosphorus) and low leakage (from carbon), effectively resolving the technical contradiction between performance improvement and harmful effect suppression.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision and control become more difficult
Solution Approach 1:
The patent changes the dopant diffusion parameter by introducing carbon as a low-diffusivity dopant alongside phosphorus. This parameter change allows for sharper dopant concentration gradients at the source/drain-channel interfaces, enabling better control of electrical characteristics even as feature sizes are reduced to increase integration density.
3Manufacturing precision
If additional source/drain layers are added to control dopant distribution, then dopant concentration control is improved, but device complexity increases
Solution Approach 1:
The patent merges the functions of multiple dopants into a single source/drain region structure. Instead of using separate layers for different dopant functions, both phosphorus and carbon are incorporated into the same source/drain region, allowing high conductivity and low leakage to be achieved simultaneously without increasing structural complexity.
Solution Approach 2:
The source/drain region is designed to perform multiple functions simultaneously: it provides high conductivity through phosphorus doping, suppresses leakage through carbon doping, and maintains structural simplicity. This multi-functionality within a single region avoids the need for additional layers while achieving precise dopant concentration control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing overall resistance and improving DC gain and oscillator speed, while maintaining high dopant concentrations, thus addressing the challenges of miniaturization.
Implementation Method 1
The use of a single material doped with low-diffusivity dopants, such as phosphorus, arsenic, and carbon, for source/drain regions in FinFETs
Data Source
AI summary
A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.