Scalable Silicon Photonic Receiver Architecture with Feedforward Equalization

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Solution Overview

Problem

Existing electro-optical communication systems face challenges with intersymbol interference (ISI) due to insufficient channel bandwidth, leading to receiver errors, and decision feedback equalizers (DFE) increase complexity without scaling well to higher throughputs.

Innovation Solution

A receiver-transmitter architecture that employs precoders to encode symbols before transmission, creating a dependency between current and previous symbols, and uses feedforward equalizers to reduce bandwidth requirements, eliminating the need for DFEs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a decision feedback equalizer (DFE) is employed to combat intersymbol interference, then ISI elimination is improved, but receiver complexity increases significantly

Engineering Contradiction:
ImproveISI eliminationVSAvoidreceiver complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The transmitter applies precoding to the transmitted symbols before they are sent through the channel. This preliminary action modifies the signal characteristics in advance, creating a dependency between current and previous symbols that allows the receiver to use a simpler feedforward equalizer instead of a complex decision feedback equalizer, thereby reducing receiver complexity while maintaining ISI elimination capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The receiver uses feedback from previous symbol decisions to adjust the equalization process. The feedforward equalizer incorporates feedback mechanisms that use previously detected symbols to refine current symbol detection, enabling effective ISI cancellation without requiring the complex structure of a DFE

Inventive Principle:
Principle #23Feedback

2Reliability

If a decision feedback equalizer (DFE) is used to eliminate intersymbol interference, then detection accuracy is improved, but scalability to higher throughputs is reduced

Engineering Contradiction:
Improvedetection accuracyVSAvoidthroughput scalability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By applying precoding at the transmitter before transmission, the system prepares the signal in advance with built-in dependencies between symbols. This preliminary action enables the receiver to maintain high detection accuracy through feedforward equalization while scaling to higher throughputs, as the precoded structure allows for more efficient signal processing compared to traditional DFE approaches

Inventive Principle:
Principle #10Preliminary action

3Reliability

If channel bandwidth is increased to prevent symbol spreading, then intersymbol interference is reduced, but power consumption increases

Engineering Contradiction:
ImproveISI reductionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The transmitter applies precoding as a preliminary action that modifies the signal spectrum and creates symbol dependencies. This allows the receiver to achieve effective ISI cancellation with a feedforward equalizer that has lower bandwidth requirements compared to traditional approaches, thereby reducing the overall power consumption of the communication system while maintaining reliable symbol detection

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12418347B2Scalable receiver architecture for silicon photonic links
Publication Date: 2025.09.16 ALTERA CORP
  • US12418347B2 patent drawing
  • US12418347B2 patent drawing
  • US12418347B2 patent drawing

AI summary

Sampling circuitry for receiving an analog signal from photodetector circuitry and generating a sample analog signal. Equalization circuitry for generating an equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap. In the equalized signal, amplitudes of the first and second sample values are substantially equal while the third sample values are attenuated relative to the first and second sample values. The first and second sample values correspond with two or more first symbols of a first alphabet. Data slicer and modulo circuitry to generate a data signal based on the equalized signal and perform a modulo operation on the two or more first symbols and to generate one or more second symbols. The second symbols are according to a second alphabet.