Silicon Photonics Chip Module for High-Bandwidth Data Transfer

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Solution Overview

Problem

Current data communication systems are inadequate for handling the high bandwidth demands of modern internet and mobile applications, particularly in transferring multimedia files, due to limitations in electrical components and channel bandwidth, which restricts data transfer speeds and interferes with symbol integrity.

Innovation Solution

The development of a high-speed electrical optics multiple chip module integrated on a single silicon substrate, utilizing silicon photonics to enhance data transfer rates by integrating optical devices closer to electrical components, including a Serializer/Deserializer block, clock data recovery block, and signal processing blocks, to achieve terabits per second speeds and support various modulation formats.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If electrical components are placed closer together to reduce channel length and inter-symbol interference, then data transfer reliability improves, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D electrical interconnects to 3D vertical stacking architecture, where multiple layers of electrical components are stacked above each other and connected via through-silicon vias (TSVs). This dimensional change allows components to be placed closer in 3D space without increasing planar complexity, reducing channel length and inter-symbol interference while maintaining manageable device complexity through vertical integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces optical components as intermediaries between electrical components, converting electrical signals to optical signals for transmission. This intermediary optical layer enables high-speed data transfer with reduced interference, as optical signals are immune to electrical noise and can traverse longer distances without degradation, thereby improving reliability without requiring extreme proximity of electrical components.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If optical devices are integrated closer to electrical devices to increase bandwidth, then data transfer speed improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedata transfer speedVSAvoidmanufacturing precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent merges electrical and optical devices into a single integrated module, where electrical components (transmitters/receivers) are directly coupled to optical components (lasers, modulators, detectors) on the same substrate. This consolidation eliminates the need for precise external alignment between separate electrical and optical modules, as the coupling interfaces are fabricated together in the same manufacturing process, thereby reducing precision requirements while enabling high-speed data transfer.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a nested architecture where optical components are embedded within or surrounded by electrical components in a hierarchical integration scheme. The optical core is nested within an electrical housing layer, with interconnects routed through dedicated vias and interlayer dielectrics. This nested structure minimizes the distance between electrical and optical interfaces while organizing the complex integration into manageable fabrication stages.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Productivity

If multiple chip module technology is used to achieve high bandwidth, then data transfer capability improves, but device complexity increases

Engineering Contradiction:
Improvedata transfer capabilityVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the communication system into distinct functional modules: electrical interface layer, optical interface layer, signal processing layer, and control layer. Each layer is independently designed and fabricated, then integrated through standardized interfaces. This segmentation allows parallel development and testing of individual modules, reducing overall system complexity while enabling high bandwidth through the combined capability of multiple specialized components working together.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution significantly increases data transfer bandwidth beyond the limitations of Moore's Law, enabling efficient transfer of large data volumes, such as terabytes, by minimizing electrical component distance and leveraging silicon photonics for improved performance in spine-leaf network architectures.

Implementation Method 1

utilizing silicon photonics to enhance data transfer rates by integrating optical devices closer to electrical components

Methodology Applied
Scientific EffectElectro-optic conversion: Electro-Optic Effects

Data Source

PatentUS9621280B2Built-in redundancy scheme for communication system on chip
Publication Date: 2017.04.11 MARVELL ASIA PTE LTD
  • US9621280B2 patent drawing
  • US9621280B2 patent drawing
  • US9621280B2 patent drawing

AI summary

In an example, the present invention includes an integrated system on chip device. The device has a redundancy block is configured to add at least redundancy bit as a function of one or more data bits associated with data for data error detection and correction data. In an example, the driver module is coupled to the signal processing blocking using a uni-directional multi-lane bus configured with N lanes, whereupon N is greater than M such that a difference between N and M represents a redundant lane or lanes. The device also has a mapping block configured to associate the M lanes to a plurality of selected laser devices for a silicon photonics device.