Silicon Photonics Layout Automation with Dummy Layer LVS
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Solution Overview
Problem
The verification of connectivity and routing quality in silicon photonics (SiPh) devices is challenging due to their diversity and differences in optical device connections, which are not adequately covered by existing product development kits (PDKs, and lack of layout versus schematic (LVS) checks for interface layers and open/shorts verification, leading to reduced layout efficiency.
Innovation Solution
An EDA system with minimal dummy layers is implemented to facilitate LVS verification for SiPh devices, using a port layer, active layer, and device layer to recognize photonic structures and apply specific LVS rules, along with an automated place and route (APR) system to automate the placement and routing of standard and custom SiPh devices, reducing the need for manual design and enhancing verification efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual design and verification methods are used for SiPh devices, then design flexibility is maintained, but layout cycle time increases and verification efficiency decreases
Solution Approach 1:
The system enables automated self-verification of SiPh device layouts through LVS checks that automatically compare layout geometry with schematic connections, eliminating the need for manual verification steps while maintaining design accuracy
Solution Approach 2:
Manual verification processes are replaced with automated electronic verification systems that use software tools to perform LVS checks, connectivity verification, and routing quality assessment without human intervention
2Reliability
If existing PDKs are used for SiPh device verification, then standard processes are maintained, but verification completeness deteriorates due to lack of interface layer and open/short verification
Solution Approach 1:
The verification process is segmented into multiple independent check layers: interface layer verification, open/short verification, connectivity verification, and routing quality verification, allowing each aspect to be verified separately and comprehensively
Solution Approach 2:
Verification rules and checklists are pre-configured for different SiPh device types (modulators, detectors, waveguides, etc.), so that when a layout is submitted, the appropriate verification checks are automatically applied without requiring manual configuration
3Measurement precision
If diverse SiPh device connections are verified manually, then connection accuracy can be maintained, but verification time increases significantly
Solution Approach 1:
The system provides automated feedback by comparing layout connections against schematic definitions and verification rules, immediately identifying mismatches, open connections, or routing errors without requiring manual inspection time
Data Source
AI summary
Silicon Photonics (SiPh) device methods and systems include providing a PDK cell library with parameters for standard SiPh device parameterized cells (Pcells). A custom SiPh layout that includes a plurality of dummy layers defining a custom SiPh device Pcell is created. A schematic including a plurality of the standard SiPh device Pcells and the custom SiPh device Pcell is created, as well as a configuration database correlating the standard SiPh device Pcells and the custom SiPh Pcell to the schematic. The standard SiPh device Pcells and the custom SiPh Pcell are automatically placed and routed based on the configuration database. A plurality of LVS rules are determined based on the dummy layers, and conducting an LVS verification is conducted based on the LVS rules.