Silicon Photonics Layout Verification Filtering
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Solution Overview
Problem
Traditional IC design verification processes, such as DRC, often generate numerous false errors when dealing with photonic structures due to their curvilinear shapes, leading to impractical manual debugging of thousands of false violations in IC layouts containing silicon photonics (SiP) components.
Innovation Solution
A computer-based method that performs SiP spacing filtering by identifying curved structures, measuring adjusted spacing values, and comparing them to constraints to differentiate between true and false SiP violations, thereby filtering out false errors without requiring customization of the foundry deck, and storing true violations for further processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRC verification processes are used on photonic structures with curvilinear shapes, then verification coverage is improved, but the number of false violations increases significantly
Solution Approach 1:
The patent segments the verification process into two distinct phases: initial DRC verification to identify all potential violations, followed by a specialized SiP filtering process that specifically targets and eliminates false violations related to curvilinear photonic structures. This segmentation allows each phase to optimize for its specific function without compromising the other.
Solution Approach 2:
The patent introduces an intermediary filtering process that acts as a mediator between the initial DRC verification and the final violation reporting. This intermediary layer specifically handles SiP-related false violations by applying curvature-aware spacing calculations, thereby protecting the final output from false positives while maintaining verification rigor.
2Measurement precision
If manual debugging is performed to verify SiP violations, then accuracy is improved, but time consumption increases excessively
Solution Approach 1:
The patent implements a self-service verification system where the filtering process automatically identifies and eliminates false SiP violations without requiring manual intervention. The system uses algorithmic curvature-based spacing calculations to autonomously distinguish true violations from false ones, thereby maintaining high accuracy while eliminating time-consuming manual debugging.
Solution Approach 2:
The patent changes the verification parameters by introducing curvature-aware spacing calculations specific to SiP structures. Instead of using standard rectilinear spacing rules, the system dynamically adjusts spacing measurements based on the curvature characteristics of photonic structures, enabling automatic accurate verification without manual intervention.
3Manufacturing precision
If rectilinear design rules are applied to photonic structures, then manufacturing precision is improved, but design flexibility is reduced
Solution Approach 1:
The patent applies local quality by implementing different verification rules for different structure types within the same design. Rectilinear structures continue to use standard DRC rules for manufacturing precision, while curvilinear SiP structures receive specialized curvature-aware verification. This localized approach allows each structure type to benefit from its optimal verification method without compromising overall design flexibility.
Solution Approach 2:
The patent explicitly accounts for curvature in SiP structures by introducing curvature-based spacing calculations. Instead of forcing all structures into rectilinear design rules, the system recognizes and accommodates curved geometries inherent to photonic structures, thereby maintaining both manufacturing precision for curved structures and design flexibility for diverse photonic applications.
Data Source
AI summary
Systems and methods for validation of photonics device layout designs. A method includes receiving, by a computer system, a rule deck and a layout design. The layout design includes silicon photonics (SiP) structures. The method includes performing a verification process to produce verification results. The verification results include violations and the violations include SiP violations. The method includes performing SiP spacing filtering to filter the SiP violations into true SiP violations and false SiP violations. The method includes storing the true SiP violations in a result database.