Silicon Photonics Unified Memory Across Multiple SoCs
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Solution Overview
Problem
Unified memory architectures in SoCs are limited to components within a single chip, preventing data transfer between GPUs in different SoCs, which reduces the benefits of unified memory in larger computing systems like servers.
Innovation Solution
Implementing a distributed unified memory system using silicon photonics to enable data sharing across multiple compute and memory die packages, connected via optical interfaces and die-to-die interconnects, allowing processors to access a unified memory architecture across multiple SoCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If unified memory architecture is implemented within a single SoC, then low latency and high bandwidth access is achieved between components, but data transfer between GPUs in different SoCs is prevented
Solution Approach 1:
The unified memory architecture is segmented across multiple SoCs, with each SoC having its own memory pool that can be accessed by other SoCs through optical interfaces. This segmentation allows the system to maintain the low-latency benefits of local memory access while enabling inter-SoC data transfer capabilities through the distributed memory pools connected via optical interconnects.
Solution Approach 2:
Optical interfaces and die-to-die interconnects serve as intermediaries between separate SoCs, enabling memory access across chip boundaries. These intermediary components facilitate direct memory access between GPUs in different SoCs while maintaining the performance characteristics of unified memory architecture.
2Productivity
If multiple memory die packages are connected via optical interfaces, then resource utilization and scalability are improved, but system complexity increases
Solution Approach 1:
The optical interfaces and memory controllers are designed with universal functionality that can handle both intra-SoC and inter-SoC memory access operations. This multi-functionality allows the same hardware components to serve multiple purposes, reducing the need for additional specialized components and thereby limiting the increase in system complexity.
Solution Approach 2:
The system transitions from a two-dimensional on-chip memory architecture to a three-dimensional distributed memory architecture using optical interconnects. This dimensional change enables scaling to multiple SoCs while maintaining manageable complexity through standardized interface protocols and modular memory die packages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables greater resource utilization and easy scaling of computing systems by allowing processors to share a distributed memory, maintaining low latency and high bandwidth access, and facilitating seamless expansion of computing capacity.
Implementation Method 1
Implementing a distributed unified memory system using silicon photonics to enable data sharing across multiple compute and memory die packages, connected via optical interfaces and die-to-die interconnects
Data Source
AI summary
Techniques are disclosed relating to computing systems that use silicon photonics. In some embodiments, a computing system includes a plurality of compute die packages that include processors configured to execute program instructions that operate on data stored in a distributed memory accessible via a unified memory architecture. The computing system further includes a plurality of memory die packages configured to implement the unified memory architecture such that a given one of the memory die packages includes one or more optical interfaces configured to receive memory requests from the processors and one or more memory controllers configured to access a portion of the distributed memory in response to the received memory requests.