Silicon Photonics Wafer Packaging with Known-Good Die Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current silicon photonics manufacturing and packaging techniques face challenges in integrating high-speed, high-bandwidth optical transceivers with compact package footprints, particularly in wafer processing, electrical and optical testing, and module assembly, which are inadequate for meeting the increasing demands of modern data communication systems.
Innovation Solution
A method for manufacturing and packaging silicon photonics wafer products that involves fabricating silicon photonics integrated circuits on a silicon-on-insulator wafer, conducting wafer-level testing, and performing post-wafer processing to create known-good-wafers for custom optical-electrical modules, including flip-bonding functional chips and aligning fiber arrays for light coupling, enabling efficient assembly of optical-electrical modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional cable communication is used, then the system is simple and cost-effective, but the bandwidth and transmission speed are limited and cannot accommodate mass information transmission
Solution Approach 1:
The patent replaces traditional electrical cable communication with optical fiber communication, substituting electrical signal transmission with optical signal transmission. This allows mass information transmission through optical carriers, achieving high bandwidth and transmission speed while overcoming the limitations of traditional cable systems
Solution Approach 2:
The patent transitions from electrical domain to optical domain by changing the fundamental transmission parameter from electrical signals to optical signals. This parameter change enables higher bandwidth utilization and faster transmission speeds through optical fiber media, directly addressing the bandwidth limitations of traditional cable communication
2Adaptability or versatility
If optical components are integrated on silicon substrates to fabricate large-scale silicon photonics integrated circuits, then the integration density and functionality increase, but the manufacturing complexity and testing difficulty increase
Solution Approach 1:
The patent combines multiple photonic components (lasers, modulators, detectors, waveguides) and electronic components into a single silicon photonics integrated circuit on a silicon substrate. This integration consolidates multiple discrete components into one unified device, achieving high integration density while managing complexity through systematic design and fabrication processes
Solution Approach 2:
The silicon photonics integrated circuit serves multiple functions simultaneously - optical signal generation, modulation, transmission, and detection - all within a single device platform. This multi-functionality approach allows the system to perform complex optical communication tasks while maintaining a compact integrated structure
3Area of stationary object
If all necessary components are integrated within smaller silicon photonics chips to decrease package footprint, then the compactness increases, but the manufacturing and testing challenges in wafer level increase
Solution Approach 1:
The patent segments the integration process into distinct phases: wafer-level fabrication of multiple identical circuit patterns, wafer-level testing of arrays of chips, and subsequent packaging. This segmentation allows standardized mass production of compact circuits while managing testing complexity through automated wafer-level processes before final packaging
Solution Approach 2:
The patent transitions from individual chip processing to wafer-level processing, adding the dimension of parallel manufacturing. By fabricating and testing multiple identical circuit patterns simultaneously on a single wafer, the system achieves compact package footprints while managing manufacturing complexity through high-volume parallel processing
4Reliability
If wafer-level testing is implemented to identify known-good-wafers, then the quality control and yield improve, but the processing time and cost increase
Solution Approach 1:
The patent performs comprehensive electrical and optical testing at the wafer level before dicing individual chips, identifying known-good-wafers and known-good-dies in advance. This preliminary quality control prevents defective chips from proceeding to subsequent packaging and assembly steps, improving overall yield while managing time through efficient automated testing processes
Data Source
AI summary
A method of packaging the silicon photonics wafer for fabricating custom optical-electrical modules includes fabricating a wafer with multiple dies of silicon photonics circuits based on custom design and conducting electrical and optical tests of the silicon photonics circuits in wafer level. The method further includes preparing the wafer for next point of use. Additionally, the method includes performing post-wafer processing on the wafer received at the next point of use. The method further includes conducting post-process electrical tests of the silicon photonics circuits in wafer level. Furthermore, the method includes preparing the wafer with known-good-dies or a known-good-wafer identified for custom use. Moreover, the method includes performing custom process on the know good dies.