Silicon Photonics Optical Waveguide Alignment
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Solution Overview
Problem
Existing optical waveguide devices face challenges in achieving high positional accuracy between silicon waveguides of silicon photonics chips and core layers of optical waveguides, which affects the efficient transmission and reception of optical signals.
Innovation Solution
The optical waveguide device comprises a first and second silicon photonics chip, an optical waveguide with a core layer and cladding layers, and an encapsulation resin. The core layer is directly formed on the silicon waveguides with high accuracy using alignment marks, and the cladding layers and encapsulation resin provide additional support and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate manufacturing and joining of silicon photonics chip and optical waveguide are used, then manufacturing flexibility is improved, but positional accuracy between silicon waveguides and core layers deteriorates
Solution Approach 1:
The patent merges the silicon photonics chip and optical waveguide into a single integrated structure where the core layer is directly formed on the silicon waveguide. This integration eliminates the separate joining process, thereby maintaining manufacturing flexibility while significantly improving positional accuracy between the silicon waveguide and core layer.
Solution Approach 2:
The patent employs preliminary action by forming alignment marks on the silicon photonics chip before forming the core layer. These pre-established alignment marks guide the precise formation of the core layer, ensuring high positional accuracy is achieved during the manufacturing process without compromising manufacturing flexibility.
2Manufacturing precision
If direct formation of core layer on silicon waveguide is used, then positional accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the optical waveguide structure into distinct functional layers: the silicon waveguide layer, the core layer, and the cladding layer. This segmentation allows each layer to be optimized and formed independently with specific functions, achieving high positional accuracy while managing device complexity through modular layering.
Solution Approach 2:
The patent introduces alignment marks as intermediary elements that facilitate the precise formation of the core layer on the silicon waveguide. These alignment marks serve as mediators that enable high positional accuracy without requiring direct complex interactions between the core layer formation process and the silicon waveguide structure.
3Manufacturing precision
If multiple cladding layers are stacked, then alignment and support are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent addresses alignment challenges by transitioning to a vertical stacking dimension, where multiple cladding layers are stacked on top of each other. This vertical arrangement provides additional alignment references and support structures, improving alignment accuracy while the layer-by-layer formation process manages manufacturing complexity.
Solution Approach 2:
The patent implements a nested structure where the first cladding layer is positioned between the silicon photonics chip and the second cladding layer. This nesting arrangement provides progressive support and alignment references at different levels, improving alignment accuracy while organizing the manufacturing process in a systematic sequence.
Data Source
AI summary
An optical waveguide device includes a first and a second silicon photonics chip, an optical waveguide, and an encapsulation resin. The optical waveguide includes a core layer and a first and a second cladding layer. The core layer has a first and a second end portion optically coupled with a first and a second silicon waveguide, respectively, on surfaces of the first and the second silicon photonics chip. The first cladding layer covers a surface of the core layer between the first and the second end portion, and is thinner than the first and the second silicon photonics chip. The second cladding layer is stacked on the first cladding layer and covers the surfaces of the first and the second silicon photonics chip and the core layer. The encapsulation resin is stacked on the first cladding layer and covers the first and the second silicon photonics chip.