Silicon PUF Element Using Off-State MIS Transistors
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Solution Overview
Problem
Existing silicon Physical Unclonable Function (PUF) devices face high power consumption issues, making them unsuitable for integration into small circuits like Integrated Circuits (IC) tags, necessitating a PUF technique with lower power consumption.
Innovation Solution
A semiconductor device incorporating fin-type Field Effect Transistors (FET) as Metal Insulator Semiconductor (MIS) transistors in a series configuration to create a PUF element that outputs high or low signals based on the potential of a connection node, reducing power consumption and stabilizing output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional silicon PUF devices (Arbiter PUF, Ring Oscillator PUF) are used, then authentication function is achieved, but power consumption becomes too large for integration into small circuits like IC tags
Solution Approach 1:
The patent changes the operational state parameter of the MIS transistors from active to off-state, fundamentally altering how the PUF function is achieved. By utilizing threshold voltage variations in the off-state rather than active-state current flow, the invention reduces power consumption while maintaining authentication reliability through intrinsic physical property variations.
Solution Approach 2:
The patent replaces the mechanical/electrical operation of transistors in active state with a static off-state configuration. Instead of using current flow or oscillation (mechanical/electrical motion), the invention uses the static threshold voltage characteristics of off-state transistors, substituting dynamic operation with static property measurement to reduce power consumption.
2Use of energy by stationary object
If MIS transistors are configured in series in off-state, then power consumption is reduced, but output signal stability must be maintained
Solution Approach 1:
The patent introduces asymmetry by coupling capacitors with different capacitance values (C1 and C2) to the series-connected MIS transistors. This asymmetric capacitor configuration ensures that the voltage division at the connection node produces stable and distinguishable output signals based on the threshold voltage variations of the transistors, while maintaining the low-power off-state operation.
Solution Approach 2:
The patent uses capacitors as intermediary elements to couple the off-state MIS transistors to the output node. These capacitors mediate the signal transmission, allowing the threshold voltage variations of the transistors to be converted into stable output voltage levels without requiring the transistors to be in active state, thus maintaining both low power consumption and signal stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves lower power consumption and stabilizes output signals, enabling high-speed operation and efficient integration into small circuits while minimizing power usage.
Implementation Method 1
by using variations of the properties in the individual semiconductor elements, intrinsic identification information can be output from the semiconductor circuits of the same design
Data Source
AI summary
In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in off-state coupled in series, as a PUF element. The PUF element outputs a signal of high level or low level depending on the potential of a connection node of the first and the second MIS transistors. Preferably, the MIS transistors are fin-type FETs.