Silicon Recess Etch Uniformity via HBr-Enhanced Plasma
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Solution Overview
Problem
The uniformity of recess etch processes in semiconductor integrated circuits is compromised by non-uniform lateral etch variations due to loading effects from neighboring geometries, leading to inconsistent transistor channel lengths and carrier mobility across the integrated circuit.
Innovation Solution
A plasma etch process using a combination of fluorine-based or chlorine-based primary etchant species with hydrogen bromine added at a 1:1 ratio, under etchant-starved conditions, to control the undercut of gate structures and reduce loading effects, followed by epitaxial filling with stress-inducing silicon-germanium or silicon-carbon alloys.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plasma etch processes are used for recess etching, then the etching can be completed, but non-uniform lateral etch variations occur due to loading effects from neighboring geometries
Solution Approach 1:
The patent modifies the plasma etch process parameters by introducing hydrogen bromide (HBr) gas at specific flow rates (2-5 sccm) in combination with primary etchants (SF6, NF3, or Cl2) at controlled flow rates (2-4 sccm). This parameter change transforms the etching chemistry to reduce loading effects and achieve more uniform lateral etch profiles across different geometries. The specific gas composition and flow rate ratios create etchant-starved conditions that minimize the impact of neighboring feature densities on etch uniformity.
Solution Approach 2:
Hydrogen bromide (HBr) acts as an intermediary substance in the plasma etch process. It mediates between the primary etchant species and the silicon substrate, modifying the etching mechanism to reduce loading effects. The HBr introduces bromine radicals that interact with silicon to form volatile SiBr4, providing a more uniform etch rate that is less sensitive to local geometry variations and feature density.
2Productivity
If etchant flow rates are increased to improve etching speed, then productivity increases, but lateral etch uniformity deteriorates due to enhanced loading effects
Solution Approach 1:
The patent optimizes the balance between etching speed and uniformity by carefully controlling the flow rates of all gases. The primary etchant flow rates are limited to 2-4 sccm and HBr flow rates to 2-5 sccm, creating etchant-starved conditions. This parameter configuration maintains acceptable etching speed while ensuring that the etch rate is governed by the controlled arrival of reactive species rather than by local geometry, thereby achieving uniform lateral etch profiles.
Solution Approach 2:
The patent employs partial action by using sub-saturated etchant concentrations. Instead of providing excess etchant that would lead to non-uniform loading effects, the process uses controlled, limited amounts of reactive species (etchant-starved conditions) that ensure uniform consumption across the substrate surface, prioritizing uniformity over maximum etching speed.
3Reliability
If recess etch undercut is increased to accommodate fabrication variations, then manufacturing robustness improves, but transistor channel length control precision deteriorates
Solution Approach 1:
The patent uses modified plasma etch parameters (HBr addition, controlled flow rates) to achieve a more predictable and uniform undercut profile. The etchant-starved conditions create consistent lateral etching behavior that is less sensitive to local variations in feature density, resulting in more uniform undercut dimensions across different transistor locations while maintaining the necessary undercut for fabrication robustness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves uniform transistor performance by minimizing the variation in undercut etch, allowing for precise control of strain induction in channel regions, thereby enhancing carrier mobility and reducing performance degradation across the integrated circuit.
Implementation Method 1
A plasma etch process using a combination of fluorine-based or chlorine-based primary etchant species with hydrogen bromine added at a 1:1 ratio
Implementation Method 2
fluorine-based or chlorine-based primary etchant species with hydrogen bromine added at a 1:1 ratio, under etchant-starved conditions, to control the undercut of gate structures
Implementation Method 3
followed by epitaxial filling with stress-inducing silicon-germanium or silicon-carbon alloys
Data Source
AI summary
A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.