Silicon Recess Etch and Epitaxial Deposit for Shallow Trench Isolation
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Solution Overview
Problem
Conventional shallow trench isolation (STI) processes often result in over-etching during acidic wet etching, leading to etching defects that affect the electrical integrity of semiconductor devices, including altering threshold voltage and making them susceptible to reverse short channel effects.
Innovation Solution
A recess etch process followed by epitaxial growth is employed to reduce the surface portion of active regions, constraining the epitaxial layer laterally by STI structures, thereby reducing uncontrolled strain and eliminating divots that occur due to over-etching, and a multi-step dry etch process is used to form uniform fins in FinFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If acidic wet etching is used to form STI trenches, then etching speed is improved, but etching precision deteriorates due to over-etching and divot formation
Solution Approach 1:
The etching process is divided into two distinct stages: a first etching process that removes the majority of the trench depth, and a second etching process that completes the trench formation with higher precision. This segmentation allows each process to be optimized independently - the first process for speed and the second for precision, thereby resolving the contradiction between etching speed and precision.
2Reliability
If recess etch depth is increased to eliminate divots, then STI structure integrity is improved, but threshold voltage control deteriorates due to excessive material removal
Solution Approach 1:
The etching process incorporates feedback mechanisms through precisely controlled etch parameters and sequential processing steps. The first etching process is controlled to remove material down to a specific depth, and the second etching process is controlled to achieve the final precise depth. This feedback-controlled approach ensures that sufficient material is removed to eliminate divots while maintaining precise control over the final etch depth to preserve threshold voltage characteristics.
3Device complexity
If conventional single-step etching is used, then process complexity is reduced, but fin uniformity deteriorates due to loading effects
Solution Approach 1:
The etching process is divided into a first etching process and a second etching process, where each process targets specific aspects of trench formation. The first process addresses bulk material removal, while the second process addresses precision finishing. This segmentation enables better control over loading effects and improves fin uniformity, with the added benefit that the processes can be independently optimized without significantly increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces threshold voltage mismatch, eliminates uncontrolled strain, and ensures uniform fin thickness, enhancing the electrical performance and reliability of semiconductor devices by minimizing the adverse effects of over-etching and improving photolithography and inter-level gap-fill processes.
Implementation Method 1
An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure
Implementation Method 2
A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure
Data Source
AI summary
Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.