Silicon Resonator Package Layout for Low Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing packaging technologies for small piezoelectric resonators face challenges in achieving smaller sizes with improved temperature resistance and reduced manufacturing tolerances, leading to potential short-circuits and increased static capacity, which are not satisfactorily addressed by traditional metal or ceramic cases.
Innovation Solution
A silicon-on-insulator package design with a base part and wall made from doped and non-doped silicon, respectively, featuring conductive vias insulated by dielectric linings and an insulating partition to minimize static capacity, achieved through photolithographic and etching processes like DRIE, and further reduced by adding an insulating partition to series with parallel capacities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If silicon packaging is used to achieve better dimensional tolerances, then manufacturing precision is improved, but static capacity increases significantly
Solution Approach 1:
The base part is divided into two electrically isolated zones by an insulating partition, separating the conductive regions around each via from each other. This segmentation prevents the formation of large parallel capacitance paths while maintaining the conductive connections needed for electrical functionality.
Solution Approach 2:
An insulating partition is introduced as an intermediary element between the two conductive vias in the base part. This partition acts as a dielectric barrier that blocks direct electrical connection between the vias through the base, thereby reducing parasitic capacitance while still allowing mechanical support and precise positioning.
2Volume of moving object
If package size is reduced to meet miniaturization requirements, then volume is decreased, but manufacturing tolerances become more critical and risk of short-circuits increases
Solution Approach 1:
The invention changes the electrical parameters of the base part by introducing insulating partitions, transforming it from a fully conductive structure to a segmented structure with controlled electrical isolation. This allows smaller package dimensions while maintaining reliable electrical connections and preventing short-circuits through the insulating barriers.
3Strength
If metal cases are used for packaging, then strength is improved, but availability in SMD versions and size reduction are limited
Solution Approach 1:
The invention changes the material parameter from metal to silicon, enabling SMD compatibility and size reduction. The silicon base part maintains sufficient mechanical strength while allowing precise photolithographic patterning and smaller dimensions. The conductive properties of doped silicon replace the need for metal cases.
4Ease of manufacture
If ceramic cases are used for packaging, then SMD compatibility is achieved, but size is limited by production technology and tolerances
Solution Approach 1:
The invention replaces the traditional mechanical ceramic packaging system with a silicon-based system that uses photolithographic and etching processes. This substitution enables much smaller dimensions and tighter tolerances by leveraging semiconductor manufacturing capabilities rather than traditional ceramic processing limitations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the overall static capacity by a factor of 10, achieving values comparable to ceramic packages while maintaining better dimensional tolerances and avoiding short-circuits, thus enhancing the reliability and performance of the resonator packaging.
Implementation Method 1
each of the conductive vias being surrounded by a insulating lining so as to insulate said vias from the main portion of the base part
Implementation Method 2
This better dimensional tolerance results from the use of a semiconductor photolithographic process and an etching technique such as DRIE
Implementation Method 3
an etching technique such as DRIE (Deep Reactive Ion Etching)
Implementation Method 4
The silicon base part 11 includes two conductive vias 16a and 16b arranged to connect the inside piezoelectric resonator 14
Implementation Method 5
packaging for piezoelectric resonators
Data Source
Figure 1~3
Figure 4~6
AI summary
The invention concerns an assembly comprising a piezoelectric resonator (14) and a case (10), the case including a base part (11), on which the resonator is mounted, a wall (12) extending from said base part so as to surround at least partially said resonator, and a cover fixed to said wall in such a way as to close said case. The base part includes a main portion (17) and at least two conductive vias (16a, 16b). The conductive vias electrically connect The piezoelectric resonator to an outside circuit through the base part, and each of the conductive vias is surrounded by a insulating lining (18) so as to insulate the vias from the main portion (17). The main portion (17) of the base part (11) is divided into two parts by an insulating partition (21) in such a way that the two conductive vias are on different sides of the partition.