Silicon Ribbon FET VC Image Simulation for Reference-Free Defect Detection
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is compounded by the constraints on lithographic processes used to pattern these building blocks, leading to a trade-off between feature dimension and spacing.
Innovation Solution
Implementing voltage contrast (VC) image simulation capability and associated test structures, which utilize electron beam inspection techniques to predict voltage contrast brightness levels based on metal connectivity, allowing for defect detection without a reference VC image, and enabling efficient defect analysis through layout search and connectivity modeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down below 10 nanometer node, then increased density of functional units is achieved, but maintaining mobility improvement and short channel control becomes difficult
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional multi-gate structures (tri-gate, gate-all-around). By adding vertical dimensions and wrapping gates around channels, the invention achieves better electrostatic control and short channel effects at scaled dimensions without sacrificing device density.
Solution Approach 2:
The patent employs composite material structures including silicon-germanium (SiGe) sacrificial layers combined with silicon nanowire channels, and high-k dielectric materials combined with metal gate electrodes. These composite structures enable precise control of channel properties and threshold voltages while maintaining scalability.
2Reliability
If multi-gate and nanowire transistor structures are implemented, then short channel control is improved, but lithographic process constraints increase
Solution Approach 1:
The patent uses preliminary sacrificial nanowire structures formed via atomic layer deposition (ALD) and chemical vapor deposition (CVD) to define future transistor locations. These sacrificial structures guide subsequent self-aligned processing steps, eliminating the need for multiple lithographic patterning operations and reducing lithographic constraints.
Solution Approach 2:
The patent implements self-aligned gate formation where gates automatically position themselves relative to channel structures through sequential deposition and etching steps. The gate material conformally coats the channel structures, and subsequent isotropic etching releases the gates into their final positions without requiring additional lithographic alignment, thereby simplifying the lithographic process.
3Productivity
If voltage contrast image simulation is implemented, then defect detection speed is improved, but measurement precision may be affected
Solution Approach 1:
The patent creates simulated voltage contrast images based on extracted process parameters from actual manufacturing data. These simulated images serve as reference copies that can be rapidly generated and compared against new inspection data, enabling fast defect detection while maintaining accuracy through parameter-driven simulation rather than exhaustive reference image storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates rapid defect detection and reduces scan time by predicting VC brightness levels, eliminating the need for a reference VC image, and enhancing the robustness and efficiency of defect analysis in integrated circuit fabrication.
Implementation Method 1
utilize electron beam inspection techniques to predict voltage contrast brightness levels
Data Source
AI summary
Voltage contrast (VC) image simulation capability and associated test structures are described. In an example, an integrated circuit structure has layouts of differing brightness when exposed to an e-beam.