Silicon Rich Capping Layer Pre-Amorphized with Germanium and Boron
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Solution Overview
Problem
The challenge in fabricating transistors lies in achieving low PMOS contact resistivity while maintaining thermal stability, particularly in scaling down multi-gate and nanowire transistors, where conventional methods face limitations due to trade-offs between feature size and spacing, and the use of titanium contacts on SiGe results in high contact resistivity and thermal instability.
Innovation Solution
A silicon rich capping layer pre-amorphized with germanium and boron implants is used to create a protective layer on PMOS source/drain structures, which provides thermal stability and low contact resistivity by incorporating boron as active dopants and minimizing Schottky barriers, and cryogenic implants are employed to minimize end-of-range damage and achieve sharp interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to fabricate transistors, then manufacturing simplicity is maintained, but PMOS contact resistivity is high and thermal stability is poor
Solution Approach 1:
The patent applies preliminary action by pre-amorphizing the silicon-rich capping layer with germanium and boron implants before contact formation. This pre-treatment modifies the material properties in advance, enabling the layer to serve dual purposes: reducing contact resistivity and providing thermal stability during subsequent processing steps.
Solution Approach 2:
The patent employs composite materials by creating a silicon-rich capping layer doped with both germanium and boron. This composite structure combines the benefits of silicon-rich material (thermal stability) with boron doping (low contact resistivity) and germanium enhancement (improved material properties), achieving superior performance compared to conventional single-material approaches.
2Productivity
If feature size is scaled down to increase device density, then device capacity increases, but short channel control and mobility improvement deteriorate
Solution Approach 1:
The patent applies local quality by implementing a silicon-rich capping layer specifically at the contact regions with high boron concentration. This localized doping strategy provides low contact resistivity where needed without adversely affecting the channel properties, enabling continued scaling while maintaining device performance through spatially differentiated material composition.
3Ease of manufacture
If titanium contacts are used on SiGe, then manufacturing is simplified, but contact resistivity is high and thermal stability is poor
Solution Approach 1:
The patent applies parameter changes by modifying the material composition and doping concentration of the capping layer. By creating a silicon-rich layer with high boron concentration (1E19 to 1E21 atoms/cm³) and adding germanium, the contact properties are fundamentally changed to achieve low resistivity and thermal stability, moving away from conventional titanium-on-SiGe parameters.
Solution Approach 2:
The patent replaces conventional titanium contacts with a composite silicon-rich capping layer doped with boron and germanium. This composite material provides both low contact resistivity and thermal stability, overcoming the limitations of titanium-SiGe contacts while maintaining ease of manufacture through integration with existing capping layer processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in PMOS contact resistivity of approximately 2e-9 Ohm cm² with thermal stability, enhancing transistor performance and drive currents, and is compatible with high-volume manufacturing for GAA and finFETs.
Implementation Method 1
A silicon rich capping layer pre-amorphized with germanium and boron implants is used to create a protective layer on PMOS source/drain structures
Implementation Method 2
cryogenic implants are employed to minimize end-of-range damage and achieve sharp interfaces
Implementation Method 3
provides thermal stability and low contact resistivity by incorporating boron as active dopants
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A
AI summary
Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.