Silicon-Rich-Oxide Liner for High Aspect Ratio Gapfill
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Solution Overview
Problem
Current high aspect ratio gap filling in semiconductor processing using high density plasma chemical vapor deposition (HDP CVD) faces challenges such as void formation, overhangs, and damage to underlying structures due to directional deposition and sputtering processes, especially in narrow features with high aspect ratios, which complicates the filling of small features without leaving voids or compromising device performance.
Innovation Solution
A multi-step process involving HDP CVD of a dielectric layer followed by deposition of an etch selectivity layer and subsequent etch back using sputter and reactive plasma etching to reduce voids and top hats, with the etch selectivity layer being chosen for resistance to sputter etch but ease of chemical etch, allowing for improved gap filling without damaging the underlying structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If HDP CVD is used for high aspect ratio gapfill, then bottom-up deposition is achieved, but overhangs and voids form at the entry region
Solution Approach 1:
A liner layer is deposited beforehand on the sidewalls and entry region of the gap before the main dielectric fill. This preliminary layer prevents overhang formation by providing a protective barrier that reduces sputtering and redeposition effects during the HDP CVD process, thereby eliminating voids at the entry region while maintaining bottom-up deposition.
Solution Approach 2:
The liner layer acts as an intermediary between the incoming plasma species and the gap structure. It mediates the interaction by absorbing excess sputtered material and preventing it from forming overhangs, thus resolving the contradiction between achieving bottom-up fill and avoiding harmful overhang formations.
2Manufacturing precision
If multi-step deposition/etch back process is used to remove overhangs, then gap fill quality improves, but throughput decreases significantly
Solution Approach 1:
The liner layer is deposited continuously in the same HDP CVD chamber along with the main dielectric fill, eliminating the need for separate deposition and etch back steps. This continuous process maintains high throughput while achieving void-free gap fill, as the liner prevents overhang formation during the deposition itself rather than requiring post-processing removal.
Solution Approach 2:
The harmful overhang formation mechanism is extracted and addressed by introducing the liner layer, which removes the need for subsequent etch back steps. By taking out the problem at its source during deposition, the process eliminates multiple process steps and maintains high throughput.
3Manufacturing precision
If sputtering is used to remove material from trench top, then directional bottom-up fill is enabled, but damage to underlying structure occurs
Solution Approach 1:
The liner layer serves as a cushioning protective layer deposited beforehand on the underlying structure. During sputtering operations, this liner absorbs the impact of ion bombardment and prevents damage to the underlying dielectric and device structures, while still allowing the directional bottom-up fill to proceed effectively.
Solution Approach 2:
The liner layer acts as an intermediary that mediates between the sputtering process and the underlying structure. It allows the necessary sputtering for directional control to occur while protecting the sensitive underlying structures from damage, thus resolving the contradiction between achieving directional deposition and preventing structural damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process significantly reduces the incidence of voids and weak spots in high aspect ratio gaps, enabling reliable filling of narrow features with reduced damage to the underlying structure, improving throughput and device performance.
Implementation Method 1
HDP CVD deposits more material at the bottom of a high aspect ratio structure than on its sidewalls. It accomplishes this by directing charged dielectric precursor species downward, to the bottom of the gap
Implementation Method 2
removing deposited material from the trench top through sputtering by the use of biased RF power applied to the substrate
Implementation Method 3
removing deposited material from the trench top through sputtering by the use of biased RF power applied to the substrate
Implementation Method 4
the etch selectivity layer is removed by substantially isotropic chemical dry etching
Data Source
AI summary
In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots is provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. Prior to etch back, the feature gap is plugged with an etch selectivity layer. The etch back part of the process involves multiple steps including a sputter etch to reduce the top hat formations followed by a reactive plasma etch to open the gap. This method improves gapfill, reduces the use of high cost fluorine-based etching and produces interim gaps with better sidewall profiles and aspect ratios.