Silicon Stack Semiconductor Package Assembly Using Phase Change Materials
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Solution Overview
Problem
Conventional through-silicon vias (TSV) packages require multiple reflows, leading to reliability issues with solder bumps and increased manufacturing time, as they do not utilize a one-time reflow process to both reflow solder bumps and cure support structures.
Innovation Solution
A one-time reflow process using phase change materials, such as epoxy, is employed to reflow solder bumps and cure or vaporize support structures, ensuring alignment and adhesion of stacked semiconductor dies during the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If multiple reflows are performed to solidify solder bumps and cure interposers/spacers, then adhesion and structural integrity are improved, but reliability of solder bumps deteriorates and manufacturing time increases
Solution Approach 1:
The patent combines the reflow process for solder bumps and the curing process for interposers/spacers into a single integrated reflow step. The support pins are made of temperature-sensitive material that cures at the reflow temperature range (180-220°C), allowing simultaneous solidification of solder bumps and curing of structural components, thereby reducing multiple reflows to one and improving solder bump reliability
Solution Approach 2:
The invention uses temperature-sensitive material for support pins that undergoes phase change or chemical reaction at specific temperature ranges. By controlling the reflow temperature parameters to match the curing point of the support pin material, the patent achieves curing of interposers/spacers and solidification of solder bumps simultaneously through parameter optimization
2Strength
If multiple reflows are performed to solidify solder bumps and cure interposers/spacers, then adhesion and structural integrity are improved, but manufacturing time increases
Solution Approach 1:
The patent merges multiple separate thermal processing steps (solder reflow and spacer/interposer curing) into a single reflow operation. The support pins are designed to cure within the standard reflow temperature range, eliminating the need for separate post-curing steps and reducing total manufacturing time while maintaining structural integrity
Solution Approach 2:
The support pins are pre-configured with temperature-sensitive material that will automatically cure during the standard reflow process. This preliminary preparation of the support pin material allows it to perform dual functions: providing mechanical support during assembly and automatically curing during the necessary reflow step, thereby eliminating additional curing steps
3Manufacturing precision
If conventional methods use separate reflows for interposer-substrate and die-interposer coupling, then alignment precision is maintained, but process complexity increases
Solution Approach 1:
The patent integrates the alignment and coupling functions into a single reflow process. The support pins with temperature-sensitive material provide mechanical alignment during the reflow step, and the simultaneous curing of these pins ensures precise positioning while reducing the number of process steps. This eliminates the need for separate reflow operations and their associated alignment procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances reliability and reduces manufacturing time by aligning and interconnecting semiconductor dies in a single reflow step, while allowing the phase change materials to cure or evaporate, thereby fixing the dies in place.
Implementation Method 1
A one-time reflow process using phase change materials, such as epoxy, is employed to reflow solder bumps and cure or vaporize support structures
Implementation Method 2
heating the semiconductor dies and the substrate to cause the second semiconductor die to become electrically interconnected to the first semiconductor die and the first semiconductor die to become electrically connected to the substrate
Data Source
AI summary
A method of manufacturing a plurality of stacked die semiconductor packages, including: placing a phase change material between a top surface of a substrate and a bottom surface of a first die; placing a phase change material between a top surface of the first die and a bottom surface of a second die; wherein the first and second dies have a plurality of conductive protrusions on the bottom surfaces of the dies; wherein the first die has a plurality of conductive vias extending from its conductive protrusions, through the first die, to the top surface of the first die; wherein the conductive vias of said first die are in alignment with the conductive protrusions of the second die; and heating the dies and the substrate to cause the second die to become electrically interconnected to the first die and the first die to become electrically connected to the substrate.