Silicon Package for Stacked Semiconductor Chips
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Solution Overview
Problem
Conventional semiconductor devices face challenges with thermo-mechanical stresses due to material mismatches, parasitic resistances and inductances, and manufacturing costs, particularly in power switching devices like power blocks and converters, which require miniaturization and improved reliability in varying environmental conditions.
Innovation Solution
A semiconductor package structure and fabrication method using low-grade silicon slabs as both the carrier and package, eliminating leadframes, bonding wires, and plastic encapsulation, and employing etching and metal deposition techniques to stack chips directly onto circuit boards, minimizing thermal expansion mismatches and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional plastic encapsulation and leadframe structures are used, then device assembly is straightforward, but thermo-mechanical stresses cause delamination and reliability degradation
Solution Approach 1:
The patent uses a silicon carrier substrate with the same material composition as the semiconductor chips, creating a homogeneous structure throughout. This eliminates the thermo-mechanical stress caused by material mismatches between different components, preventing delamination and improving long-term device stability under temperature variations.
Solution Approach 2:
The patent extracts and eliminates the problematic plastic encapsulation and leadframe components from the conventional package structure. By removing these heterogeneous materials that cause thermal expansion mismatches, the invention directly addresses the source of thermo-mechanical stress while maintaining protective and functional capabilities through the silicon carrier.
2Reliability
If bonding wires and clips are used for electrical connections, then chip interconnections are achieved, but parasitic inductance and resistance increase
Solution Approach 1:
The patent merges the electrical connection function directly into the carrier substrate by fabricating metal traces and contact pads on the silicon carrier itself. This integration eliminates the need for separate bonding wires and clips, reducing parasitic inductance and resistance while improving electrical performance and signal integrity.
Solution Approach 2:
The silicon carrier substrate serves as an intermediary that provides both mechanical support and electrical connectivity. The metal traces deposited on the carrier act as intermediate conductors between chip contacts, replacing the function of bonding wires while minimizing parasitic effects through optimized trace geometry and material selection.
3Adaptability or versatility
If multiple discrete components are assembled horizontally, then functionality is achieved, but device footprint and complexity increase
Solution Approach 1:
The patent transitions from horizontal side-by-side assembly to vertical stacking architecture. Multiple semiconductor chips (power MOSFETs, diodes, controller) are stacked vertically on the silicon carrier, enabling three-dimensional integration. This dimensional change dramatically reduces the device footprint while maintaining all required power conversion functionalities.
Solution Approach 2:
The silicon carrier substrate performs multiple functions simultaneously: it provides mechanical support, thermal management, electrical interconnection through metal traces, and structural integration for stacked chips. This multi-functionality eliminates the need for separate leadframes, substrates, and packaging materials, reducing overall device complexity and footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermo-mechanical stresses, minimizes parasitic resistances and inductances, enhances thermal conductivity, and enables concurrent miniaturization of power blocks and converters, improving reliability and reducing manufacturing costs while maintaining high electrical performance.
Implementation Method 1
The use of widely different materials such as metals, ceramics, and plastics cause challenges not only for mutual parts adhesion, but also for long-term device stability; an example is delamination of adjacent parts. For plastic-packaged semiconductor devices, extensive research has been dedicated to identify corrective measures for device reliability issues caused by thermo-mechanical stress due to material-based mismatches of the coefficients of thermal expansion
Implementation Method 2
employing etching and metal deposition techniques to stack chips directly onto circuit boards
Implementation Method 3
employing etching and metal deposition techniques to stack chips directly onto circuit boards
Implementation Method 4
enhances thermal conductivity, and enables concurrent miniaturization of power blocks and converters
Data Source
AI summary
An electronic system comprises a first chip of single-crystalline semiconductor shaped as a hexahedron and including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by retaining walls, and including a second electronic device. The container shaped as a slab bordered by the retaining walls and including conductive traces and terminals. The first chip is attached to the slab of second chip, forming nested chips. The first and second chips embedded in the container. The nested first and second chips are operable as an electronic system and the container is operable as the package of the system.