Silicon Substrate Modification for Strained Germanium Channel Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistors scale down to smaller dimensions, imparting strain on channel regions to enhance charge carrier mobility becomes ineffective due to poor mechanical coupling between the channel and source/drain regions, and the use of a Si substrate limits the ability to form different strained materials, leading to suboptimal performance in CMOS applications.
Innovation Solution
A thin, relaxed Ge-based layer is formed on a modified Si substrate using a modification layer to serve as a template for growing compressively strained PMOS and tensile strained NMOS channel materials, achieving improved hole and electron mobility by efficiently managing defects and preventing their propagation to the surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a Si substrate is used to form strained channel materials, then device performance can be improved through strain, but the ability to form different strained materials is limited due to lattice mismatch
Solution Approach 1:
A Ge-based buffer layer is introduced as an intermediary between the Si substrate and the strained channel materials. This buffer layer has a lattice constant intermediate between Si and the strained materials, enabling the formation of both compressively strained PMOS and tensile strained NMOS channel materials on the same Si substrate without excessive lattice mismatch
Solution Approach 2:
The lattice constant of the buffer layer is specifically selected to be intermediate between Si and the strained channel materials. By changing the material parameter (lattice constant) of the buffer layer, the system enables the formation of different strained materials that would otherwise be incompatible with direct Si substrate integration
2Productivity
If transistors are scaled down to smaller dimensions, then device density and integration are improved, but mechanical coupling between channel and source/drain regions deteriorates making strain ineffective
Solution Approach 1:
The approach changes from relying on mechanical strain (which becomes ineffective at small dimensions) to relying on material composition and interface quality. By using a Ge-based buffer layer with specific lattice parameters and forming high-quality interfaces, the system maintains effective charge carrier mobility enhancement even when mechanical coupling is poor
3Stability of the object's composition
If a thin Ge-based layer is formed on Si substrate, then relaxed Ge-based layer can be achieved, but defects propagate to the surface reducing layer quality
Solution Approach 1:
The thickness of the Ge-based buffer layer is optimized to a specific range that allows sufficient relaxation while preventing defect propagation to the surface. By controlling this critical parameter, the system achieves both relaxation and high surface quality
Solution Approach 2:
The buffer layer is designed with specific local properties including controlled thickness, composition gradient, and defect management characteristics. This local optimization allows the buffer layer to provide relaxation benefits at the interface while maintaining high quality at the surface where the channel materials will be formed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the growth of high-quality, fully strained channel materials with reduced leakage and increased drive currents, enhancing the performance of PMOS and NMOS devices and facilitating their co-integration in CMOS circuits.
Implementation Method 1
A thin, relaxed Ge-based layer is formed on a modified Si substrate using a modification layer to serve as a template for growing compressively strained PMOS and tensile strained NMOS channel materials
Data Source
AI summary
An integrated circuit (IC) includes a substrate that includes silicon. A first layer is on the substrate and includes a first monocrystalline semiconductor material, the first layer having a plurality of defects. A second layer is on the first layer and includes a second monocrystalline semiconductor material that includes germanium. A strained channel structure is above the first layer. A gate structure is at least above the channel structure. A source region is adjacent the channel structure. A drain region is adjacent the channel structure, such that the channel structure is laterally between the source region and the drain region.


