Crystalline Silicon TFT Films with Staged SiGe Crystallization
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Solution Overview
Problem
Existing methods for fabricating polycrystalline silicon thin film transistors (TFTs) face issues such as high operational costs, defects like 'scan mura' in AMOLED displays, and inadequate performance due to intra-grain and grain boundary defects in solid phase crystallization (SPC) poly Si films, limiting display resolution and device yield.
Innovation Solution
A method involving the formation of multiple silicon layers with controlled doping and annealing to initiate crystallization away from the substrate interface, reducing defect density by lateral and vertical crystal growth, and forming TFTs with reduced-defect density polysilicon films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If excimer laser annealing (ELA) is used to crystallize amorphous silicon, then crystalline silicon film is obtained for TFT fabrication, but high operational costs and scan-mura defects occur in AMOLED displays
Solution Approach 1:
The patent divides the crystallization process into multiple stages by forming multiple amorphous silicon layers with different doping concentrations. The heavily doped layer crystallizes first at lower temperature, followed by the intrinsic layer, creating a segmented crystallization sequence that eliminates laser scanning and prevents scan-mura defects while maintaining crystalline quality
Solution Approach 2:
The patent performs preliminary doping of silicon layers before crystallization, creating layers with different crystallization temperatures. This preliminary action allows the heavily doped layer to crystallize first and provide a template for subsequent crystallization of the intrinsic layer, achieving defect-free crystallization without laser scanning
2Object-generated harmful factors
If solid phase crystallization (SPC) is used to crystallize amorphous silicon, then scan-mura defects are eliminated, but intra-grain and grain boundary defects reduce TFT performance
Solution Approach 1:
The patent applies local quality by creating regions with different doping concentrations within the silicon structure. The heavily doped layer serves as a nucleation region with different crystallization properties, while the intrinsic layer provides high-quality active channel material, optimizing both defect reduction and TFT performance in different locations
Solution Approach 2:
The heavily doped silicon layer acts as an intermediary that facilitates crystallization of the intrinsic silicon layer. It provides nucleation sites and a crystallization template that guides the growth of the intrinsic layer, reducing intra-grain and grain boundary defects while maintaining excellent TFT performance
3Object-generated harmful factors
If multiple TFTs and capacitors are used in pixel circuits to compensate for TFT characteristic differences, then scan-mura appearance is reduced, but display resolution is limited and device yield decreases
Solution Approach 1:
The patent converts the potential harm of simple pixel circuits into a benefit by ensuring uniform TFT characteristics through controlled crystallization. The multi-layer structure with sequential crystallization produces highly uniform TFTs that perform consistently with simple 2T1C circuits, turning what would normally require complex compensation circuits into a straightforward design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces crystalline defect density, improves TFT performance, enhances display resolution, and increases production yield by minimizing defects and scan-mura, while using simpler pixel circuits.
Implementation Method 1
annealing at an elevated temperature to induce crystallization of the amorphous silicon layers
Implementation Method 2
annealing at an elevated temperature to induce crystallization of the amorphous silicon layers
Implementation Method 3
crystallization of the amorphous silicon layers, with the crystallization propagating laterally and vertically through the layers
Data Source
AI summary
A method of producing a reduced-defect density crystalline silicon film includes forming a Six1Ge1-x1 film on a substrate, forming a Six2Ge1-x2 film on the Six1Ge1-x1 film, forming a silicon film on the Six2Ge1-x2 film, and annealing to crystallize the Six1Ge1-x1, Six2Ge1-x2, and silicon films. The values of x1 and x2 are between zero and one. The Six1Ge1-x1 and Six2Ge1-x2 films are amorphous at formation, having a first thermal budget and a second thermal budget, respectively, for crystallization, the second thermal budget lower than the first thermal budget, the Six2Ge1-x2 film spaced apart from the substrate by the Six1Ge1-x1 film. A crystalline silicon TFT device includes a substrate, a crystallized Six1Ge1-x1 layer on the substrate, a crystallized Six2Ge1-x2 layer on the crystallized Six1Ge1-x1 layer, a crystallized silicon layer on the Six2Ge1-x2 layer, a gate insulator layer on the crystallized silicon layer, and a gate electrode on the gate insulator layer.