Silicon Through Electrode Coplanarity via Preliminary Formation
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Solution Overview
Problem
Existing electronic component packages with cavities in silicon substrates face challenges in achieving sufficient coplanarity of through electrodes, leading to faulty connections and reduced yield, especially when trying to integrate various elements, due to the difficulty in planarizing electrodes after cavity formation and forming fine wiring layers.
Innovation Solution
The solution involves forming through electrodes in a flat silicon substrate before creating a cavity, allowing for easy planarization and then using a frame portion from a second silicon substrate to construct the cavity, ensuring the electrodes' coplanarity and enabling low-temperature joining without damaging the electrodes, thus facilitating the integration of various elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If through electrodes are formed after cavity formation in silicon substrate, then cavity structure is achieved, but coplanarity of through electrodes deteriorates
Solution Approach 1:
The patent applies preliminary action by forming through electrodes in the silicon substrate before creating the cavity structure. This sequence allows the through electrodes to be formed on a flat surface, ensuring good coplanarity, and then the cavity is formed subsequently without affecting the electrode alignment and flatness.
2Manufacturing precision
If through electrodes are planarized after cavity formation, then coplanarity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent eliminates the need for post-cavity planarization by performing the through electrode formation before cavity creation. This preliminary action ensures coplanarity is achieved during the electrode formation process itself, avoiding the need for additional CMP or other planarization steps that would increase manufacturing complexity.
3Manufacturing precision
If fine wiring layers are formed on cavity bottom surface, then connection precision is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent forms fine wiring layers on the flat upper surface of the silicon substrate before cavity formation, rather than attempting to form them on the cavity bottom surface. This preliminary action on a flat surface significantly reduces manufacturing difficulty while maintaining high connection precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures sufficient coplanarity of through electrodes even with a cavity, improves the reliability of electronic component mounting, and allows for the easy integration of various elements, enhancing the yield and cost-effectiveness of the manufacturing process.
Implementation Method 1
an insulating layer 400 made of a silicon oxide layer is formed on the whole surface of the silicon wafer 100 by thermally oxidizing the silicon wafer 100
Implementation Method 2
through electrodes 500 are formed in the through holes TH in the silicon wafer 100 by the plating
Data Source
Figure 1A~1D
Figure 1E~1G
Figure 2A~2E
AI summary
An electronic component package, comprises: a package substrate portion (11) constructed by a first silicon substrate (10a) in which a through hole (TH) is provided, a first insulating layer (14) formed on upper and lower surface sides of the first silicon substrate (10a) and inner surface of the through hole (TH), and a through electrode (18) filled in the through hole (TH); and a frame portion (23) formed from a second silicon substrate (20a), the frame portion (23) defining an opening extending from an upper surface to a lower surface of the frame portion (23) and being stacked on top of a peripheral portion of the package substrate portion (11) to constitute a cavity (C) on the first silicon substrate (10a) wherein the through electrode (18) is positioned. An upper surface of the through electrode (18) is coplanar with an upper surface of the first insulating layer (14) formed on the upper surface side of the first silicon substrate (10a). The frame portion (23) includes an element (ZD) formed on a lower surface side of the second silicon substrate (20a), a connection electrode (56) formed under the element (ZD) and connected electrically to the element (ZD), and a second insulating layer (54) formed on a periphery of the connection electrode (56). The connection electrode (56) of the frame portion (23) is directly joined to the through electrode (18) of the package substrate portion (11).