Direct Silicon Tiling of Image Sensor Arrays
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Solution Overview
Problem
Current methods for manufacturing large tiled arrays of CMOS image sensors with fiber optic faceplate attachments or high planarity for X-ray panels are costly, labor-intensive, and result in high sensor failure rates and low yield due to un-flat surfaces and complex assembly processes.
Innovation Solution
The direct silicon tiling assembly process involves aligning and flattening semiconductor dies on a vacuum plate to achieve coplanarity, followed by attachment to printed circuit boards and either a fiber optic or vacuum plate, allowing for improved surface flatness and reduced assembly time and labor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sensor die are attached to ceramic printed circuit board substrates without planarization, then assembly is easier and sensor die natural convex bow is preserved, but the resulting stacked structure has unpredictable flatness profile causing sensor failure, bubble formation, and very long process times
Solution Approach 1:
The patent applies preliminary planarization action to the sensor die before attachment to the ceramic substrate. A planarization layer is deposited over the convex bow of the sensor die to create a flat surface, ensuring uniform epoxy thickness and preventing subsequent assembly defects such as bubble formation and sensor failure.
Solution Approach 2:
The patent introduces a planarization layer as an intermediary between the sensor die and the epoxy layer. This intermediate layer compensates for the convex bow of the sensor die, providing a flat mounting surface that enables proper FOP attachment while preserving the sensor die's natural structure.
2Manufacturing precision
If custom assembly process with micro-manipulation and holding frame is used, then sensor tiles can be aligned and locked in place, but labor hours, equipment development costs, and assembly time are not optimized for cost effective manufacture
Solution Approach 1:
The patent extracts and eliminates the complex holding frame and micro-manipulation equipment from the assembly process. By using pre-planarized sensor die that attach uniformly to the ceramic substrate, the need for expensive holding frames and manual micro-manipulation is removed, enabling standard automated assembly equipment to be used instead.
Solution Approach 2:
The patent enables the sensor die to self-align and self-planarize through the uniform epoxy attachment process. The pre-planarized surface of the sensor die allows it to naturally conform to the flat ceramic substrate without requiring external holding frames or complex alignment mechanisms, making the assembly process self-sufficient and easier to automate.
3Ease of manufacture
If fiber optic faceplate is attached to un-planar sensor array, then FOP assembly can be completed, but sensor failure rates are high, yield is low, and assembly cost per panel is not competitive
Solution Approach 1:
The patent applies preliminary planarization to the sensor die before FOP attachment. By creating a flat surface on the sensor die through the planarization layer, the subsequent FOP attachment process can be completed successfully without causing sensor failure or bubble formation, thereby improving yield and reducing failure rates.
Solution Approach 2:
The planarization layer serves as a protective intermediary between the FOP attachment process and the sensor die. This intermediate layer prevents direct mechanical stress and potential damage to the sensor die during FOP attachment, reducing sensor failure rates and improving overall assembly reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process minimizes yield loss and assembly time, enhances panel reliability, and reduces labor costs by addressing un-flat surfaces and complex assembly issues, potentially improving yield by 25-50% and reducing labor hours by 50-100%.
Implementation Method 1
aligning a plurality of image sensor dies into the tiled array on a vacuum plate that is subjected to a vacuum, and the flattening flattens all image sensor dies in the tiled array against the vacuum plate with the vacuum
Data Source
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AI summary
A method of making a tiled array of semiconductor dies includes aligning and flattening. One end of each semiconductor die has attached thereto a respective printed circuit board. The aligning aligns the semiconductor dies into the tiled array in such a way that the semiconductor dies rest on a vacuum plate and the one end of each die extends beyond an edge of the vacuum plate. The flattening flattens the semiconductor dies against the vacuum plate with a vacuum after the semiconductor dies are aligned.