Silicon Wafer BMD Morphology Control for Slip and Warpage Suppression
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Solution Overview
Problem
Current silicon wafer production technologies face challenges in suppressing the generation of slip dislocations and warpage during device production, as high-temperature heat treatment induces thermal stress, leading to mechanical weakness and surface deformations, which affect semiconductor device quality and yield.
Innovation Solution
A silicon wafer production method involving specific heat treatment steps to achieve BMDs with a diagonal length of 10 nm to 50 nm and a density of at least 1×10^11/cm^3 at depths greater than 50 μm, along with a {111} plane ratio of less than 0.3, to effectively suppress slip and warpage, while maintaining wafer strength and enabling high-quality semiconductor device production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-temperature heat treatment is performed to form DZ layer, then crystal defects near surface are eliminated, but oxygen concentration decreases due to outward diffusion and slip dislocation extends from surface
Solution Approach 1:
The patent applies preliminary action by forming BMDs with specific morphology (low {111} plane ratio) and high density in the bulk region BEFORE device formation processes. This pre-established defect structure serves as a buffer that prevents slip dislocation extension from the surface during subsequent heat treatments, while the DZ layer is still formed to eliminate surface defects. The preliminary BMD configuration ensures that even when oxygen diffuses outward during DZ layer formation, the bulk BMDs remain available to suppress slip extension.
Solution Approach 2:
The patent segments the wafer into functionally distinct regions: a surface DZ layer (0-50μm depth) with eliminated crystal defects for device formation, and a bulk region (50μm+ depth) with high-density BMDs for slip suppression. This spatial segmentation allows each region to perform its specific function independently - the DZ layer provides defect-free surface for devices while the bulk BMDs provide mechanical stability and prevent slip extension, resolving the contradiction between surface quality and bulk strength.
2Strength
If BMD density is increased to suppress slip dislocation, then wafer strength improves, but thermal stress during heat treatment increases causing warpage
Solution Approach 1:
The patent applies local quality by creating different BMD characteristics in different depth regions. The bulk region (50μm+ depth) has high BMD density (≥1×10^11/cm³) with specific morphology (low {111} plane ratio ≤0.3) optimized for slip suppression, while the surface region maintains a DZ layer with eliminated defects for device formation. This localized differentiation allows the bulk to provide strength through BMDs while the surface remains defect-free, and the controlled BMD morphology minimizes thermal stress-induced warpage during heat treatment.
3Manufacturing precision
If DZ layer is formed by high-temperature annealing, then surface defects are reduced, but slip dislocation extends from contact points with susceptor
Solution Approach 1:
The patent applies preliminary action by establishing a bulk BMD network (density ≥1×10^11/cm³ at 50μm+ depth with low {111} plane ratio) BEFORE performing high-temperature annealing to form the DZ layer. This pre-configured bulk defect structure acts as a containment field that prevents slip dislocation generated at susceptor contact points during DZ layer formation from extending into the device formation region. The preliminary bulk BMDs compensate for the slip generation that inevitably occurs during subsequent surface annealing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces slip dislocation and warpage generation, ensuring high-quality silicon wafers with enhanced mechanical strength and gettering capability, suitable for large-diameter wafers and various semiconductor devices, such as epitaxial and SIMOX wafers, by controlling BMD morphology and density.
Implementation Method 1
supersaturated oxygen taken into the silicon lattice in a supersaturated state, which causes formation of micro defects known as Bulk Micro Defects (BMD), during a subsequent heat treatment (anneal)
Implementation Method 2
results in an extreme decrease of oxygen concentration by outward diffusion of oxygen during heat treatment
Implementation Method 3
generation of a temperature gradient on the silicon wafer surface causes thermal stress on the surface in proportion to the gradient
Data Source
AI summary
A silicon wafer includes BMDs with a diagonal length of from 10 nm to 50 nm, and has a density of BMD which exists at a depth of 50 μm and deeper from the surface of the silicon wafer which is greater than or equal to 1×1011/cm3, and a ratio of the {111} plane of the BMD to the total planes surrounding the BMD, as an indication of the morphology of the BMD, is less than or equal to 0.3.