Silicon Wafer Carbon Doping for Stacking Fault Reduction
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Solution Overview
Problem
The challenge is to reduce the density of stacking faults (SF) in silicon epitaxial layers of low-resistivity silicon wafers, particularly for larger 300 mm wafers, where existing methods are ineffective in inhibiting the generation of dislocation loop defects that lead to SF formation.
Innovation Solution
The solution involves growing silicon wafers with specific thermal history conditions, including adjusting the residence time at the temperature zone where SF nuclei are formed, and incorporating carbon as a dopant to inhibit the cohering of interstitial silicon, thereby reducing the density of large dislocation loop defects. This is achieved by growing a 300 mm single crystal ingot with phosphorus doping and performing argon annealing to reduce carbon diffusion and dislocation loop formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the resistivity of the silicon wafer is reduced to 0.9 mΩ·cm or less, then the electrical conductivity is improved, but stacking faults are generated in the silicon epitaxial layer during epitaxial growth
Solution Approach 1:
The patent applies preliminary action by performing high-temperature heat treatment (argon annealing at 1150-1250°C for 10-120 minutes) on the silicon wafer before epitaxial growth. This pre-treatment modifies the crystal structure and reduces dislocation loop defects in advance, preventing stacking fault generation during subsequent epitaxial growth while maintaining the low resistivity of 0.9 mΩ·cm or less
Solution Approach 2:
The patent changes physical parameters by controlling the residence time of the single crystal ingot at 570°C±70°C during crystal growth to 100-500 seconds, and by conducting argon annealing at 1150-1250°C. These parameter changes suppress dislocation loop formation and enable low-resistivity silicon wafers (0.9 mΩ·cm or less) to produce epitaxial layers with stacking fault density of 5000/cm² or less
2Manufacturing precision
If the residence time at the temperature zone where SF nuclei are formed is extended, then the crystal growth completeness is improved, but the density of dislocation loop defects increases
Solution Approach 1:
The patent optimizes the residence time parameter at the SF nucleation temperature zone (570°C±70°C) to a specific range of 100-500 seconds during single crystal ingot growth. This parameter change achieves the optimal balance between crystal growth completeness and suppression of dislocation loop defect formation, preventing excessive defect generation while ensuring proper crystal structure development
3Reliability
If carbon concentration is increased to inhibit dislocation loop formation, then the quality of epitaxial layer is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent controls carbon concentration within a specific range of 3.5×10¹⁵ to 5×10¹⁷ atoms/cm³ during single crystal growth. This parameter control achieves effective suppression of dislocation loop defects and improves epitaxial layer quality without requiring overly complex manufacturing processes, maintaining industrial feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach significantly reduces the density of dislocation loop defects and subsequent SF generation in the epitaxial layer, enhancing the quality of the silicon wafer for epitaxial growth and preventing defects in the epitaxial layer, thereby improving the resistivity and gettering performance of the wafer.
Implementation Method 1
incorporating carbon as a dopant to inhibit the cohering of interstitial silicon, thereby reducing the density of large dislocation loop defects
Implementation Method 2
performing argon annealing to reduce carbon diffusion and dislocation loop formation
Implementation Method 3
performing argon annealing to reduce carbon diffusion and dislocation loop formation
Implementation Method 4
when an epitaxial growth process is performed
Data Source
AI summary
A silicon wafer is provided in which a dopant is phosphorus, resistivity is 1.2 mΩ·cm or less, and carbon concentration is 3.5×1015 atoms/cm3 or more. The carbon concentration is decreased by 10% or more near a surface of the silicon wafer compared with a center-depth of the silicon wafer.