Silicon Wafer Doping Homogeneity via Partial Compensation
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Solution Overview
Problem
Silicon semiconductor devices face challenges in achieving a balance between high electrical breakdown voltage and low on-state resistance, with issues like avalanche breakdown and undesired inversion channel formation due to segregation effects during Czochralski method growth, which affect device robustness and reliability.
Innovation Solution
A silicon ingot and wafer with a drift zone of net n-type doping partially compensated by p-type dopants, maintaining a consistent electrically active net doping concentration through axial gradients, reducing carrier mobility and inversion channel formation by adjusting doping concentrations using boron and other p-type dopants with varying segregation coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If silicon is doped with donors during Czochralski growth, then net n-type doping concentration increases, but doping homogeneity deteriorates due to segregation effects
Solution Approach 1:
The patent changes the doping parameters by introducing p-type dopants (acceptors) in addition to n-type dopants (donors), and by controlling their respective segregation coefficients through selective doping during different growth stages. This allows achieving homogeneous net doping concentration despite the inherent segregation effects in Czochralski growth
Solution Approach 2:
The patent creates a composite doping structure by combining both n-type and p-type dopants in the silicon crystal. The interaction between donors and acceptors with different segregation coefficients compensates for segregation effects, resulting in improved doping homogeneity while maintaining the required net n-type concentration
2Reliability
If high net n-type doping concentration is used, then on-state resistance decreases, but avalanche breakdown voltage and device reliability worsen
Solution Approach 1:
The patent applies different doping strategies to different regions of the drift zone. By controlling the axial gradient of doping concentration and using partial compensation with p-type dopants, the patent creates optimal local doping conditions that prevent avalanche breakdown and inversion channel formation while maintaining low on-state resistance
Solution Approach 2:
The patent introduces p-type dopants as a preliminary countermeasure to prevent the harmful effects of high n-type doping. The p-type dopants compensate for excess n-type doping and prevent inversion channel formation at interfaces before these harmful effects can occur during device operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the robustness and reliability of silicon semiconductor devices by minimizing avalanche breakdown and inversion channel formation, improving the homogeneity of doping concentrations and specific resistance along the ingot axis, thus optimizing device performance.
Implementation Method 1
silicon is heated in a crucible to the melting point of silicon at around 1416° C. to produce a melt of silicon
Implementation Method 2
Molten silicon freezes on the silicon seed crystal. By slowly pulling the silicon seed crystal away from the melt, a crystalline silicon ingot is grown
Implementation Method 3
Growing of silicon with defined doping by the Czochralski method is complicated by segregation effects. The segregation coefficient of a dopant material characterizes the relation between the concentration of the dopant material in the growing crystal and that of the melt
Data Source
AI summary
A method of manufacturing a silicon wafer includes extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants, adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%, and slicing the silicon ingot.