Silicon Wafer Dislocation Testing with Edge-Effect Exclusion
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Solution Overview
Problem
Current methods for assessing the resistance of semiconductor wafers to thermally induced dislocations are not simple, reliable, or reproducible, as they are influenced by edge effects and vary in test conditions.
Innovation Solution
A method involving a heat treatment in a vertical furnace with a long finger boat, where the distance between support points and the wafer edge is tailored to prevent edge effects, combined with BFA analysis using a SIRD system to evaluate dislocation resistance, ensuring consistent and reproducible results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor wafer is subjected to heat treatment in a vertical furnace with fingers at standard positions, then the test can be performed using conventional equipment, but edge effects influence the test result and reduce reliability
Solution Approach 1:
The patent applies local quality by positioning the fingers at specific distances from the wafer edge (5-40% of diameter) rather than uniformly distributing them. This creates different local conditions: the region near the edge (within 1-33% of diameter) is excluded from evaluation to avoid edge effects, while the central region provides reliable dislocation data. The evaluation is locally focused on areas away from edge influences.
2Area of stationary object
If the distance between support points and wafer edge is reduced, then more support points can be used increasing test coverage, but edge effects begin to influence the test result
Solution Approach 1:
The patent changes the critical parameter of finger positioning distance from the wafer edge to a specific range (5-40% of diameter). This parameter optimization allows the evaluation area to extend sufficiently far from the edge to capture dislocation patterns while maintaining reliability by excluding the immediate edge region (1-33% from edge) from evaluation. The parameter change balances coverage and reliability.
3Measurement precision
If the heat treatment temperature is increased to induce dislocations, then the test sensitivity increases, but the critical stress changes and results become less reproducible
Solution Approach 1:
The patent optimizes the heat treatment temperature parameter to a specific range (900-1200°C) rather than using arbitrarily high temperatures. This controlled parameter change ensures sufficient dislocation induction for sensitive detection while maintaining reproducibility by avoiding temperatures that cause excessive critical stress variations. The parameter is tailored to the specific semiconductor material properties.
4Measurement precision
If the duration of heat treatment is extended to induce more dislocations, then the test sensitivity improves, but the dislocations may propagate to the edge and contaminate the measurement
Solution Approach 1:
The patent takes preliminary action by pre-calculating and pre-setting the evaluation exclusion zone (1-33% from edge) before conducting the heat treatment. This preliminary definition of the evaluation boundary ensures that even if dislocations propagate toward the edge during extended heat treatment, they will not contaminate the measurement data. The safe zone is established in advance based on expected dislocation propagation distances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for a reliable and reproducible assessment of semiconductor wafers' resistance to thermally induced dislocations, focusing on the properties of the material and optimizing heat treatment conditions to induce dislocations within specific areas for accurate characterization.
Implementation Method 1
US2004 0 021 097 A1 describes a way in which SIRD (Scanning Infrared Depolarization) can be used to investigate mechanical stresses in semiconductor wafers
Implementation Method 2
heat treatments of semiconductor wafers in a vertical furnace can cause thermally induced dislocations
Data Source
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AI summary
A method for testing the resistance of single-crystal silicon semiconductor wafers to thermally induced dislocations, comprising subjecting a semiconductor wafer to a heat treatment in a vertical furnace tailored to the properties of the semiconductor material, wherein the semiconductor wafer has a diameter and rests on bearing points of a number of fingers of a boat and a distance of the bearing points to an edge of the semiconductor wafer has a length that is not less than 5% and not more than 40% of the diameter of the semiconductor wafer; performing a BFA analysis of one or more sub-areas of the semiconductor wafer around the bearing points using a SIRD system, wherein the shortest distance of the one or more sub-areas to the edge of the semiconductor wafer is not less than 1 mm and not more than 33% of the diameter of the semiconductor wafer.