Silicon Wafer Defect Control via Pulling Rate Optimization
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Solution Overview
Problem
Existing methods for manufacturing silicon single crystal wafers using the Czochralski method often result in crystal defects, such as oxidation-induced stacking faults and grown-in defects, which degrade device performance and hinder the formation of a defect-free Denuded Zone (DZ) layer and oxide precipitates, essential for gettering sites in semiconductor devices.
Innovation Solution
A method involving the Czochralski method for growing silicon single crystal ingots, followed by rapid thermal annealing with controlled pulling rates and heat treatment temperatures to ensure the entire wafer area becomes a neutral region, thereby preventing vacancy agglomeration and ensuring a sufficient DZ layer on the surface while forming oxide precipitates in the bulk as gettering sites.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the Czochralski method is used to grow silicon single crystal, then silicon single crystal ingot can be manufactured, but crystal defects such as oxidation-induced stacking faults and grown-in defects are generated
Solution Approach 1:
The patent applies parameter changes by precisely controlling the pulling rate during crystal growth to maintain the entire wafer area in the N region. By adjusting the pulling rate parameter, the concentration distribution of vacancies and interstitial silicon is optimized to prevent defect formation while maintaining manufacturing feasibility through the CZ method.
Solution Approach 2:
The patent employs preliminary action by pre-establishing the appropriate N region conditions during the crystal growth phase before wafer fabrication. By controlling the pulling rate to create the proper concentration distribution of point defects in advance, the foundation for a defect-free DZ layer is laid before subsequent processing steps.
2Productivity
If the pulling rate is increased, then productivity is improved, but vacancy-type defects such as COP and FPD are generated in the crystal
Solution Approach 1:
The patent resolves this contradiction by optimizing the pulling rate parameter to a specific range that maintains the entire wafer area in the N region. This optimized parameter setting prevents vacancy supersaturation and subsequent defect formation while achieving high productivity, eliminating the need to trade off between speed and quality.
3Reliability
If the pulling rate is decreased to eliminate defects, then crystal quality is improved, but manufacturing efficiency is reduced
Solution Approach 1:
The patent achieves both high crystal quality and manufacturing efficiency by identifying and implementing an optimized pulling rate parameter. This parameter ensures the entire wafer area remains in the N region, preventing defect formation while maintaining sufficiently high growth speed for practical production, thus eliminating the need to sacrifice productivity for quality.
4Reliability
If a DZ layer is formed without defects, then device performance is improved, but it becomes difficult to form oxide precipitates for gettering sites
Solution Approach 1:
The patent applies local quality by creating different regions with different properties: the DZ layer near the surface maintains a defect-free structure with appropriate vacancy concentration for high device performance, while the bulk region contains oxide precipitates for gettering. This spatial differentiation of properties allows both objectives to be achieved simultaneously in different locations within the same wafer.
Solution Approach 2:
The patent segments the wafer into functionally distinct regions: a defect-free DZ layer in the active region near the surface and a bulk region with oxide precipitates for gettering. This segmentation allows each region to be optimized for its specific function while being part of the same crystal structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively secures a defect-free surface layer with a sufficient DZ layer and promotes the formation of oxide precipitates in the bulk, enhancing device properties like oxide dielectric breakdown voltage and improving yield and productivity by preventing vacancy-type defects and ensuring efficient oxygen precipitation.
Implementation Method 1
a silicon single crystal is grown by a Czochralski method
Implementation Method 2
a silicon single crystal is grown by a Czochralski method
Implementation Method 3
the obtained silicon single crystal ingot is subjected to a rapid thermal annealing
Implementation Method 4
oxidation-induced stacking fault called OSF which is generated in a ring shape while being subjected to thermal oxidation processing
Data Source
Figure 1
Figure 2(a)~2(c)
Figure 3
AI summary
The present invention provides a method for manufacturing a silicon single crystal wafer in which a silicon single crystal ingot is pulled by a CZ method, and a wafer sliced from the ingot is subjected to a rapid thermal annealing, wherein wafers sliced from the ingot which has been pulled while changing a pulling rate are subjected to rapid thermal annealings in various heat treatment temperatures, oxide dielectric breakdown voltage measurements are performed to get a relation between the pulling rate and the heat treatment temperatures, and a result of the oxide dielectric breakdown voltage measurements in advance, conditions of a pulling rate and a heat treatment temperature are determined based on the relation so that the whole area thereof in the radial direction may become N region after the rapid thermal annealing, and the pulling of the ingot and the rapid thermal annealing are performed to thereby manufacture the silicon single crystal wafer. As a result of this, a manufacturing method capable of efficiently and certainly manufacturing the silicon wafer in which a DZ layer can be secured in a wafer surface layer and an oxide precipitate can be formed in a bulk region of the wafer is provided.