Silicon Wafer Testing Pad for Through Hole Verification
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Solution Overview
Problem
Conventional silicon wafers face issues with uneven etching rates during through hole formation, leading to small connecting areas between testing pads and seed layers, resulting in high resistance and increased manufacturing costs due to the need for slicing to verify groove penetration.
Innovation Solution
A silicon wafer with testing pads comprising multiple metal layers and interconnection metals, where a through hole is formed to expose part of the first metal layer, allowing a seed layer to be formed and resistance measured to assess connection quality, thereby increasing yield rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching is used to form through holes, then through holes can be formed in the silicon substrate, but the etching rate at the center is greater than at the periphery, resulting in an arc-shaped top and small connecting area between the pad and seed layer
Solution Approach 1:
The patent applies preliminary action by forming a groove structure in the silicon substrate before forming the through hole. This groove pre-defines the etching path and prevents excessive etching at the center, ensuring that the through hole maintains a proper shape with adequate connecting area between the pad and seed layer, thus improving both manufacturing precision and electrical reliability
Solution Approach 2:
The patent applies local quality by creating a groove with specific dimensions and shape at the location where the through hole will be formed. This localized structural modification ensures that the etching process produces a through hole with uniform wall thickness and adequate connecting area, addressing the non-uniform etching rate issue locally without affecting the entire substrate
2Reliability
If grooves are formed to surround the seed layer for electrical insulation, then the seed layer and silicon substrate can be electrically insulated, but slicing is required to verify groove penetration, increasing manufacturing cost
Solution Approach 1:
The patent introduces a testing pad as an intermediary structure that provides indirect verification of groove penetration. Instead of directly inspecting the groove (which requires costly slicing), the testing pad serves as a mediator that allows electrical measurement to confirm whether the groove properly penetrates the substrate and provides electrical insulation, thereby reducing manufacturing cost while maintaining reliability verification
Solution Approach 2:
The patent replaces the mechanical slicing inspection method with an electrical measurement method using the testing pad. By substituting the mechanical verification system (slicing and visual inspection) with an electrical measurement system (resistance measurement through the testing pad), the patent eliminates the need for costly slicing while still verifying groove penetration and electrical insulation effectiveness
Data Source
AI summary
The present invention relates to a silicon wafer having testing pad(s) and a method for testing the same. The silicon wafer includes a silicon substrate, an insulation layer, at least one testing pad and a dielectric layer. The testing pad includes a first metal layer, a second metal layer and at least one first interconnection metal. The first metal layer is disposed on the insulation layer, and has a first area and a second area. The first area and the second area are electrically insulated with each other. The second metal layer is disposed above the first metal layer. The first interconnection metal connects the second area of the first metal layer and the second metal layer. Therefore, when a through hole and a seed layer are formed in the following processes, the through hole is estimated whether it is qualified by probing the testing pad to know whether the seed layer connects the second area of the first metal layer of the testing pad, thus the yield rate of the following processes is increased.