Silicon Well Formation via Low-Temperature Epitaxy
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Solution Overview
Problem
Current methods for forming silicon wells with different crystallographic orientations in integrated circuit manufacturing face challenges such as surface defects and high-temperature annealing requirements, which hinder the formation of quality MOS transistors.
Innovation Solution
A method involving chemical vapor etching using hydrochloric acid and vapor-phase epitaxy in an epitaxy reactor at controlled temperatures and pressures to form silicon wells with orientations (110) and (100), eliminating the need for additional polishing and high-temperature annealing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxy is performed from substrate of orientation (100) into wells to form silicon with orientation (100), then the desired crystallographic orientation is achieved, but the upper silicon surface becomes non-planar requiring additional CMP polishing which induces surface defects
Solution Approach 1:
The invention changes the temperature parameter of the epitaxy process to a lower range (700-900°C) compared to conventional high-temperature epitaxy. This parameter change enables the formation of planar silicon surfaces with orientation (100) without requiring subsequent CMP polishing, thereby avoiding the induction of surface defects that would compromise MOS transistor quality
Solution Approach 2:
The invention replaces the mechanical CMP polishing process with a chemically-controlled epitaxy process. Instead of using mechanical abrasion to achieve planarity (which induces defects), the low-temperature epitaxy naturally forms planar surfaces through chemical vapor deposition, substituting a mechanical system with a chemical process that avoids harmful mechanical stresses
2Manufacturing precision
If amorphization implantation and high-temperature anneal at 1200°C are performed to extend crystallographic structure (100) into amorphized areas, then wells of different orientations can be formed, but the process requires very high temperature annealing which is difficult to implement and creates defects that are not totally eliminated
Solution Approach 1:
The invention dramatically changes the temperature parameter from very high temperature (1200°C) to a moderate range (700-900°C). This parameter change simplifies the annealing process, making it easier to implement while still achieving complete crystallization and elimination of defects, thereby resolving both the implementation difficulty and the defect elimination issues
Solution Approach 2:
The invention uses a simpler, more accessible annealing process that does not require the extreme conditions of conventional methods. The moderate temperature annealing (700-900°C) is easier to implement with standard equipment and achieves the desired result without the complexity and potential drawbacks of very high-temperature processing
3Manufacturing precision
If conventional etch and epitaxy techniques are used to form silicon with orientation (100) in wells, then the desired orientation transformation is achieved, but additional CMP polishing is required which induces surface defects preventing quality MOS transistor formation
Solution Approach 1:
The invention replaces the mechanical CMP polishing step with a chemically-controlled low-temperature epitaxy process that naturally produces planar surfaces. This substitution eliminates the mechanical stresses and surface defects induced by CMP polishing, thereby preserving MOS transistor quality while achieving the desired crystallographic orientation transformation
Solution Approach 2:
The invention makes the epitaxy process continuous by performing both the orientation transformation and surface planarization in a single uninterrupted step. The low-temperature epitaxy simultaneously achieves the crystallographic orientation change and maintains surface planarity, eliminating the need for separate polishing operations and ensuring continuous production of high-quality surfaces for MOS transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the formation of silicon wells with planar, defect-free surfaces, simplifying the process and enabling the production of high-performance P-channel and N-channel MOS transistors without inducing surface defects.
Implementation Method 1
performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.
Implementation Method 2
performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C.
Implementation Method 3
a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid
Data Source
AI summary
A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.