SIMD Affine Transformation for GF(256) Cryptographic Arithmetic
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Solution Overview
Problem
Current hardware implementations of cryptographic algorithms like AES are inefficient in terms of performance and circuit area, and existing solutions do not fully address the complexities and bottlenecks associated with cryptographic arithmetic operations, particularly in software and hardware designs.
Innovation Solution
The development of instructions and processing logic for general-purpose GF(256) SIMD cryptographic arithmetic functionality, which includes decoding instructions for affine transformations, binary finite field multiplicative inverses, and modulus reductions, enabling efficient execution on processors with SIMD capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If straightforward hardware implementations using lookup memories, truth tables, or binary decision diagrams are used for cryptographic operations, then the implementation is simple to understand and implement, but the circuit area and cost become excessive
Solution Approach 1:
The patent transforms cryptographic operations from traditional lookup-table-based approaches into polynomial arithmetic operations in GF(256). This parameter change from discrete lookup operations to algebraic operations enables more efficient hardware implementation with reduced circuit area while maintaining cryptographic security.
Solution Approach 2:
The patent replaces mechanical lookup memory access and truth table evaluation with algebraic polynomial multiplication and inversion in GF(256). This substitution eliminates the need for large lookup memories and complex truth tables, significantly reducing circuit area while preserving the cryptographic transformation functionality.
2Area of stationary object
If finite fields isomorphic to GF(256) are used for cryptographic operations, then the circuit area efficiency is improved, but the processing speed becomes slower compared to straightforward hardware implementations
Solution Approach 1:
The patent segments the cryptographic transformation into distinct polynomial arithmetic operations (multiplication, inversion, addition) in GF(256). This segmentation allows each operation to be optimized independently with dedicated hardware circuits, improving processing speed while maintaining area efficiency.
Solution Approach 2:
The patent pre-computes and stores polynomial coefficients and transformation parameters in compact lookup tables. This preliminary action allows the main cryptographic operations to proceed quickly using simple polynomial arithmetic, rather than performing complex calculations during the actual encryption/decryption process.
3Adaptability or versatility
If software implementations of cryptographic algorithms are used, then the flexibility and adaptability are improved, but the performance is orders of magnitude slower than hardware implementations
Solution Approach 1:
The patent creates a universal polynomial arithmetic framework in GF(256) that can implement multiple cryptographic operations (AES S-box, MixColumns, key expansion) using the same basic operations. This universality allows a single hardware or software implementation to handle various cryptographic functions with high performance.
Solution Approach 2:
The patent implements dynamic polynomial arithmetic operations that can adapt to different cryptographic requirements. The GF(256) operations can be configured for different modes and parameters, providing both hardware-like performance and software-like flexibility through programmable polynomial calculations.
Data Source
AI summary
Instructions and logic provide general purpose GF(28) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix is applied to each element of the source data operand, and the translation vector is applied to each of the transformed elements. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD binary finite field multiplicative inverse to compute an inverse in a binary finite field modulo an irreducible polynomial for each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.