SIMD ALU Data-Lane Reduction for Low-Bandwidth Parallel Computing
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Solution Overview
Problem
Current computer architectures, particularly in camera-based driver assistance systems, face inefficiencies in computational throughput due to the need for increased register width and memory bandwidth when processing multiple data pairs, leading to suboptimal utilization of resources in applications like image processing and computer vision.
Innovation Solution
The implementation of a SIMD arithmetic logic unit (ALU) with multiple data lanes and routing grids that allow for parallel processing of functions between pairs of data, reducing the output to a lower bit width without requiring proportional increases in register width and memory bandwidth, enabling efficient performance of operations like linear filtering, matrix multiplication, and median filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scalar processors or traditional vector processors are used to process multiple data pairs, then computational throughput is improved, but register width and memory bandwidth requirements increase proportionally
Solution Approach 1:
The ALU is segmented into multiple data lanes (first data lane, second data lane, etc.) where each lane processes a pair of data independently in parallel. This segmentation allows the system to achieve high computational throughput for processing N pairs of data without requiring proportional increases in register width, as each lane operates with its own functional units and routing resources.
Solution Approach 2:
The patent introduces a dimensional organization where data is arranged in lanes rather than using traditional flat register structures. By organizing computation along the lane dimension with multiple functional units per lane, the system achieves throughput scaling without linearly increasing the memory bandwidth dimension, effectively decoupling these two resource requirements.
2Adaptability or versatility
If increased ALU-local storage is provided to support large filters and various algorithms, then adaptability is improved, but device complexity increases
Solution Approach 1:
The routing grids and functional units are designed to be universal and reconfigurable, capable of supporting multiple algorithms including large filters, matrix operations, and various data processing functions. Rather than providing dedicated storage for each algorithm, the same hardware resources are flexibly configured through routing control to adapt to different computational requirements, maintaining low complexity while achieving high versatility.
3Ease of manufacture
If traditional routing structures are used in ALU, then ease of manufacture is maintained, but computational efficiency for parallel operations deteriorates
Solution Approach 1:
The routing structure is segmented into first routing grids and second routing grids that independently route first data and second data respectively to multiple data lanes. This segmented routing approach enables efficient parallel processing by providing dedicated routing paths for each data type to each lane, while maintaining a modular structure that is relatively easy to manufacture using standard semiconductor fabrication processes.
Data Source
AI summary
An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K′ bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J′ bits per lane, wherein J′ is less than N multiplied by K′.