SIMD ALU Data Lanes With Reduction for Low-Bandwidth Throughput
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Solution Overview
Problem
Existing computer architectures for driver assistance systems, such as camera-based systems, face inefficiencies in computational throughput due to the need for increased register width and memory bandwidth when processing multiple data pairs, leading to suboptimal utilization of resources.
Innovation Solution
The implementation of a SIMD arithmetic logic unit (ALU) with multiple data lanes that perform pairwise computations on first and second data sets, followed by a reduction operation to output a result with a reduced number of bits, allowing for efficient processing of operations like addition, subtraction, multiplication, and relational operations without storing intermediate results, thereby enhancing computational throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scalar processors are used to process multiple data pairs, then computational accuracy is maintained, but computational throughput is limited and resource utilization is suboptimal
Solution Approach 1:
The processor is divided into multiple data lanes (N lanes), each capable of independent parallel processing. Each lane processes one data pair simultaneously, enabling N-fold throughput improvement without requiring proportional increases in per-lane register width or memory bandwidth.
Solution Approach 2:
The architecture transitions from scalar (1D) processing to SIMD (N-dimensional) processing by adding the lane dimension. Multiple data pairs are processed in parallel across N lanes, effectively moving from processing single data items to processing vectors of data items simultaneously.
2Productivity
If register width and memory bandwidth are increased to process multiple data pairs, then computational throughput improves, but device complexity and resource requirements increase proportionally
Solution Approach 1:
Instead of increasing the width of single processing units, the system segments processing across N independent lanes. Each lane maintains standard register width and memory bandwidth requirements, but the aggregate throughput is N times higher due to parallel execution.
Solution Approach 2:
Each data lane is designed as a universal processing unit that can handle any data pair with standard register width. The same lane structure is replicated N times, providing multi-functionality across parallel lanes without requiring specialized wide registers or high-bandwidth memory for each lane.
3Measurement precision
If intermediate results are stored for pairwise computations, then computational accuracy is maintained, but memory bandwidth consumption and device complexity increase
Solution Approach 1:
The reduction unit merges N intermediate results from N data lanes into a single final result. Instead of storing all N intermediate values in memory, the reduction unit performs cumulative operations (addition, maximum, minimum, or sum of absolute differences) to combine results on-the-fly, significantly reducing memory bandwidth consumption.
Solution Approach 2:
The reduction unit performs self-service by immediately processing intermediate results as they become available from the data lanes. Rather than buffering all intermediate results in memory, the reduction unit continuously consumes and combines results, maintaining computational accuracy while minimizing memory bandwidth requirements.
Data Source
AI summary
An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K′ bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J′ bits per word, wherein J′ is less than N multiplied by K′.