SIMD Core Divergent Branch Handling via Hardware Pointers
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Solution Overview
Problem
In computing systems with SIMD micro-architectures, the efficiency of parallel execution is reduced due to data-dependent work items causing some execution lanes to halt while others continue, leading to idle lanes and reduced throughput, especially in scenarios with conditional branch instructions and divergent execution paths.
Innovation Solution
A processor with multiple parallel execution lanes and program counter registers that dynamically adjust instruction fetching and execution based on branch directions, allowing for simultaneous execution of instructions from different basic blocks within a variable-length instruction word, and utilizing a vector register to manage bit ranges and identifiers for efficient execution lane assignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conditional branch instructions are executed in SIMD architecture, then data-dependent work items can be processed, but execution lanes diverge causing idle lanes and reduced throughput
Solution Approach 1:
The patent segments the instruction stream into multiple basic blocks (BB0, BB1, BB2, etc.) that can be independently fetched and executed by different execution lanes. Each lane has its own program counter that can point to different basic blocks, allowing simultaneous execution of divergent paths without stalling other lanes.
Solution Approach 2:
The patent introduces a new dimension to instruction fetching by implementing variable-length Very Long Instruction Word (VLIW) that can contain instructions from multiple basic blocks. The compiler dynamically adjusts the VLIW size and composition based on which basic blocks are currently active across execution lanes, transforming the traditional single-instruction-fetch model into a multi-basic-block fetch model.
2Productivity
If variable-length VLIW is used to accommodate divergent execution paths, then all execution lanes can remain active, but instruction fetching complexity increases
Solution Approach 1:
The patent performs preliminary analysis during compilation to identify all possible basic blocks that may be executed by any execution lane. The compiler pre-determines the maximum VLIW size needed and pre-arranges instructions from different basic blocks into the variable-length VLIW structure before execution, eliminating the need for complex runtime analysis.
Solution Approach 2:
The patent introduces a compiler-generated intermediary layer that translates high-level conditional logic into variable-length VLIW instructions. This intermediary compilation step handles the complexity of managing multiple basic blocks and VLIW sizing, shielding the hardware from complexity while enabling efficient parallel execution.
Data Source
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AI summary
A system and method for efficiently processing instructions in hardware parallel execution lanes within a processor. In response to a given divergent point within an identified loop, a compiler generates code wherein when executed determines a size of a next very large instruction world (VLIW) to process and determine mulitple pointer values to store in multiple corresponding PC registers in a target processor. The updated PC registers point to instructions intermingled from different basic blocks between the given divergence point and a corresponding convergence point. The target processor includes a single instruction multiple data (SIMD) micro-architecture. The assignment for a given lane is based on branch direction found at runtime for the given lane at the given divergent point. The processor includes a vector register for mapping PC registers to execution lanes.